Semiconductor integrated circuit device having main word lines a

Details Semiconductor integrated circuit device having main word lines a Semiconductor integrated circuit device having main word lines a

2000-02-15

2000-12-12

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 63, 36518911, 365227, 36523003, G11C 808

Patent

active

061607533

ABSTRACT:
Each sub-word line drive circuit SWD in a sub-word line drive section SWLB receives a signal carried by a main word line MWL0, a sub-word line non-selection signal XWD, and a sub-word line drive signal WD to drive a sub-word line SW. The sub-word line non-selection signal XWD is generated by an inverter XWDG in an intersection region SDR based on the sub-word line drive signal WD received by the inverter. The active level of the sub-word line drive signal WD is an internal boosted potential VPP which is higher than the external supply potential VDD. By using as the inactive level of the sub-word line non-selection signal XWD an internal lowered potential VINT which is lower than the external supply potential VDD, power consumption of an internal boosted potential generation circuit is reduced.

REFERENCES:
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patent: 5966341 (1999-10-01), Takahashi et al.
M. Kinoshita et al., "Practical Low Power Design Architecture for 256 Mb DRAM", Technical Report of IEICE, DSP97-103, SDM97-141, ICD97-157, pp. 55-59, 1997-10 (English abstract).

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