Semiconductor integrated circuit device having logic macro and r

Details Semiconductor integrated circuit device having logic macro and r Semiconductor integrated circuit device having logic macro and r

1988-08-17

1989-08-08

Fears, Terrell W.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518908, 357 45, G11C 1140

Patent

active

048559580

ABSTRACT:
A semiconductor integrated circuit device has a logic macro and RAM macros, and each RAM macro has a plurality of latch circuits, an operation circuit and a memory cell array. At least one of outputs of the latch circuits within the RAM macro is coupled to the operation circuit thereof by a first interconnection when the RAM macro is used. When the RAM macro is not used, all of the outputs of the latch circuits are coupled to certain internal cells of the logic macro by a second interconnection. The first and second interconnections are determined by a function to be carried out in the circuit device, that is, designed by CAD, for example, depending on the kind or model of the circuit device.

REFERENCES:
patent: 4419746 (1983-12-01), Hunter et al.

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