Semiconductor integrated circuit device having hierarchical powe

Details Semiconductor integrated circuit device having hierarchical powe Semiconductor integrated circuit device having hierarchical powe

1997-10-17

1999-09-28

Le, Vu A.

Static information storage and retrieval

Powering

Data preservation

365226, 365 63, G11C 700

Patent

active

059599278

ABSTRACT:
A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

REFERENCES:
patent: 5270581 (1993-12-01), Nakamura
patent: 5347492 (1994-09-01), Horiguchi et al.
patent: 5541885 (1996-07-01), Takashima
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5710741 (1998-01-01), McLaury
"Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-Scale LSI'S", Masashi Horiguchi et al., 1993 Symposium on VLSI Circuit, Digest of Technical Papers, pp. 47-48.
"Stand-By/Active Mode Logic for Sub-1 VIG/4Gb DRAMS", Takashima et al., 1993 Symposium on VLSI Circuit, Digest of Technical Papers, pp. 83-84.
"A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter", Masaki Tsukude et al., International Test Conference 1992, pp. 615-622.
"1V High-Speed Digital Circuit Technology with 0.5 UM Multi-Threshold CMOS", Mutoh et al., 1993, IEEE pp. 186-189.

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