Semiconductor integrated circuit device having gate array

Details Semiconductor integrated circuit device having gate array Semiconductor integrated circuit device having gate array

1992-05-04

1994-03-01

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257202, 257203, 257207, 257210, 257211, H01L 2702, H01L 2710

Patent

active

052910431

ABSTRACT:
A gate array semiconductor integrated circuit device allowing less clock skews is disclosed. The device includes a clock signal driver formed in the part under a power supply interconnection for input-output buffer in a power supply pin region or a ground pin region. The clock signal driver is formed in the power supply pin region and so on which, conventionally, was not utilized, so that the clock signal driver can be large enough to provide a clock signal to each basic cell column. Therefore, the input-output buffer region is not unduly occupied by the clock signal driver, and the connecting pads do not become useless.

REFERENCES:
patent: 4595940 (1986-06-01), Gandini et al.
patent: 4769558 (1988-09-01), Bach
patent: 4811073 (1989-03-01), Kitamura et al.
patent: 4827368 (1989-05-01), Suzuki et al.
patent: 4883980 (1989-11-01), Morimoto et al.
Charles Ng, "A Hierarchical Floor-Planning, Placement, and Routing Tool for Sea-of Gates Designs" IEEE 1989 Custom Integrated Circuits Conference pp. 3.3.1-3.3.4.

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