Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
1999-09-17
2002-10-29
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C326S087000, C326S098000
Reexamination Certificate
active
06472917
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device having a large chip size that is provided with miniaturized wiring lines and more particularly, to a circuit configuration suitable for reducing wiring delay.
BACKGROUND ART
Conventional methods of increasing the speed of critical paths in a semiconductor integrated circuit include (A) reducing the basic delay time of gate circuits, (B) increasing the load driving force of gate circuits and (C) distributing output load by multiplexing gate circuits.
A precharge circuit is effective in the methods (A) and (B). An output node in a precharge circuit is precharged, and the precharge circuit is driven by a transistor having a low output impedance.
Although these speed increasing methods are effective on capacity load, the effect of these speed increasing methods are not as effective as expected on resistance load, such as the resistance of wiring lines.
In a conventional semiconductor integrated circuit, wiring resistance is low as compared with the on-resistance of a load driving transistor of the gate circuit. Therefore, the speed of the critical path can be increased by the speed increasing method effective in capacity load.
However, since the semiconductor integrated circuit has some long wiring lines, the necessity of increasing the speed of the long wiring lines has been understood. It has been proposed to increase the speed of long wiring lines by providing the long wiring lines with a relay buffer as mentioned in JP-A No. Hei 4-23347. The foregoing method of increasing the speed is effective when the ratio of wiring delay in the critical path is small as compared with a delay time taken by the gate circuit. However, the effect of the increase of speed decreases when the ratio of wiring delay is increased due to the enlargement of the semiconductor integrated circuit and the miniaturization of the wiring lines.
It is mentioned in connection with the effect of wiring delay in “Design of high-speed LSI”, Nikkei Electronics, No. 13, pp. 177-183, Special Edition, (March, 1995) that the ratio of wiring delay increases beyond 50% when the operating frequency exceeds 100 MHz and design rules are 0.35 &mgr;m.
Problems relating to wiring delay are contradictory to the miniaturization of semiconductor integrated circuits and the importance thereof will progressively increase in the future. At the present, the reduction of wiring delay, similarly to the increase of the speed of gate circuits, is an important problem in increasing the speed of critical paths.
A conventional method which inserts a relay buffer into a long wiring line needs inverters arranged in two stages to match the polarities of signals and is not effectively applicable to all cases for speed increase.
Accordingly, it is an object of the present invention to reduce the ratio of delay time caused by wiring resistance in a critical path included in a semiconductor integrated circuit, to increase the speed of the critical path and to improve the operating frequency of the semiconductor integrated circuit. Another object of the present invention is to increase long wiring driving speed, the distribution of noise sources by distributing long wiring line driving circuits, and to prevent the reduction of reliability due to electromigration.
DISCLOSURE OF THE INVENTION
According to the present invention, a semiconductor integrated circuit device comprises a first gate circuit, and a second gate circuit that receives an output signal provided by the first gate circuit and provides a signal to the following circuit, wherein a third gate circuit for increasing the changing speed of the output signal of the first gate circuits connected to a wiring line interconnecting the first and the second gate circuits at a position near the second gate circuit.
In this semiconductor integrated circuit device, the ratio of wiring delay due to wiring resistance in a critical path included in the semiconductor integrated circuit device is reduced and, consequently, the speed of the critical path can be increased and the operating frequency of the semiconductor integrated circuit can be improved.
REFERENCES:
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4779013 (1988-10-01), Tanaka
patent: 4973865 (1990-11-01), Haq
patent: 5057711 (1991-10-01), Lee et al.
patent: 5191245 (1993-03-01), Kang
patent: 5237213 (1993-08-01), Tanoi
patent: 5410189 (1995-04-01), Nguyen
patent: 5572151 (1996-11-01), Hanawa et al.
patent: 5654981 (1997-08-01), Mahant-Shetti et al.
patent: 5894238 (1999-04-01), Chien
patent: 6046621 (2000-04-01), Crowley
patent: 61-163414 (1986-07-01), None
patent: 63-42216 (1988-02-01), None
patent: 2-165724 (1990-06-01), None
patent: 4-23347 (1992-01-01), None
patent: 4-246913 (1992-09-01), None
patent: 8-8725 (1996-01-01), None
Kuchimachi Kazuharu
Yamauchi Tatsumi
Cunningham Terry D.
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
LandOfFree
Semiconductor integrated circuit device having compensation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device having compensation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device having compensation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2940116