Semiconductor integrated circuit device having an object circuit

Details Semiconductor integrated circuit device having an object circuit Semiconductor integrated circuit device having an object circuit

1988-04-21

1990-02-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307482, H03K 1710, H03K 357

Patent

active

049053140

ABSTRACT:
A sub-booster circuit for further stepping up an output voltage of a main booster circuit includes a first MOS transistor having a drain connected to the output terminal of the main booster circuit, and a gate connected to an input terminal of an object circuit, a second MOS transistor having a drain and a gate connected to the source of the first MOS transistor and a source connected to the input terminal of the object circuit, and a MOS capacitor having a first electrode connected to a connection node between the first and second MOS transistors and a second electrode connected to receive a clock pulse signal. A threshold voltage of the second MOS transistor is set to be larger in its absolute value than a threshold voltage of the first MOS transistor and the MOS capacitor has substantially the same threshold voltage as that of the second MOS transistor.

REFERENCES:
patent: 4382194 (1983-05-01), Nakano et al.
patent: 4398100 (1983-08-01), Tobita et al.
patent: 4511811 (1985-04-01), Gupta
patent: 4550264 (1985-10-01), Takahaski et al.
patent: 4689495 (1987-08-01), Liu
patent: 4716303 (1987-12-01), Mimoto
patent: 4725746 (1988-02-01), Segawa et al.
patent: 4731552 (1988-03-01), Miyamoto
Japanese Patent Disclosure (Kokai) No. 62-62497, Yasutaka (Mar. 19, 1987).
Yatsuda et al., "Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM," IEEE Journal of Solid-State Circuits, vol. SC-20, No. 1, pp. 144-151, Feb. 1985.

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