Semiconductor integrated circuit device having an improved verti

Details Semiconductor integrated circuit device having an improved verti Semiconductor integrated circuit device having an improved verti

1992-10-20

1995-11-21

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257518, 257593, H01L 2972

Patent

active

054689899

ABSTRACT:
There is provided a semiconductor integrated circuit device having bipolar transistors each composed of an emitter region, base region, and collector region arranged vertically on a semiconductor substrate, said collector region having a plane figure, with the square corners thereof cut off. To be concrete, the buried collector region having a high concentration of impurity has its square corners cut off and the base region formed on the major surface of the epitaxial layer formed on said buried collector region has also its square corners cut off. The bipolar transistor having such a plane figure has a reduced parasitic capacity and an increased operating speed. A manufacturing method is also provided capable of producing a highly reliable groove isolation structure with a low dielectric constant.

REFERENCES:
patent: 4546536 (1985-10-01), Anantha et al.
patent: 4654687 (1987-03-01), Hebert
patent: 4825274 (1989-04-01), Higuchi et al.
patent: 4908324 (1990-03-01), Nihira et al.
patent: 4920401 (1990-04-01), Sakai et al.
patent: 4984053 (1991-01-01), Kayanuma
Bechade et al., "Lateral PNP Transistor," IBM Technical Disclosure Bulletin, vol. 15 No. 12, May 1973, p. 3790.
Nikkei Electronics, Mar. 29, 1982, pp. 94-96 and English translation thereof.

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