Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2001-01-10
2002-03-19
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S541000, C323S316000
Reexamination Certificate
active
06359494
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device which has a reference current generating circuit independent particularly from a power supply voltage Vcc.
FIG. 1
is a circuit diagram showing the conventional reference current generating circuit. In this circuit, a P-channel MOS transistor Qp
1
, a N-channel MOS transistor Qn
1
, a resistor R
1
, and a N-channel MOS transistor Qn
2
are connected in series between a power supply voltage Vcc and a ground GND. The gate of the transistor Qp
1
is supplied with a starting signal V
start
for controlling the circuit to turn from the stand-by state to the active state. The gate of the transistor Qn
1
is applied with a reference voltage V
ref
generated by the external circuit. The gate of the transistor Qn
2
is connected to a drain thereof so as to constitute a diode. The transistor Qn
2
outputs an output V
out
from the gate to make a reference current I
ref
which is equal to the current flowing into Qn
2
through the resistor R
1
, flow from a N-channel MOS transistor Qn
6
(Qn
6
has substantially the same characteristics and size as those of Qn
2
) which is connected to form a current mirror circuit with the transistor Qn
2
.
When the voltages at the both ends of the resistor R
1
are respectively denoted as V
1
and V
2
, the current value I
ref
is determined by the values of V
1
and V
2
. In the circuit constituted as above, V
1
depends on the reference voltage and the threshold voltage of the transistor Qn
1
, and V
2
depends on the threshold voltage of the transistor Qn
2
. The potentials V
1
and V
2
are thus determined by the reference voltage V
ref
and the threshold voltages V
th
of the transistors Qn
1
and Qn
2
, as represented by the following equations:
V
1
=
V
ref
−V
th
V
2
=
V
th
(1)
Hence, the current value I
ref
is represented as follows:
I
ref
=(
V
1
−
V
2
)/
R
1
=(
V
ref
−2
V
th
)/
R
1
(2)
where R
1
is the resistance value of the resistor R
1
.
As is clear from the above equation (2), the current value I
ref
is represented by the equation which does not include the term of the power supply voltage Vcc. The current value I
ref
is determined by the reference voltage V
ref
, the threshold voltage V
th
of the transistors, and the resistance value R
1
. This circuit is thus independent from the influence of the power supply voltage Vcc.
FIG. 2
is a circuit diagram showing the constitution of the conventional oscillation circuit using the reference current generating circuit shown in FIG.
1
. This circuit is basically the same as that disclosed in U.S. Pat. No. 5,627,488. The elements shown in
FIG. 1
are denoted by the same reference numerals.
A capacitor C
1
has one end connected selectively to either of the power supply voltage Vcc and the drain of the N-channel MOS transistor Qn
6
in accordance with the level of the voltage of the common gate of a N-channel transistor Qn
45
and a P-channel transistor Qp
20
. Similarly, a capacitor C
2
has one end connected selectively to either of the power supply voltage Vcc and the drain of the N-channel MOS transistor Qn
7
in accordance with the voltage level of the common gate of a N-channel transistor Qn
46
and a P-channel transistor Qp
21
.
P-channel MOS transistors Qp
14
-Qp
16
and N-channel MOS transistors Qn
38
-Qn
4
O constitute a first amplifier A
1
for comparing the reference voltage V
ref
and the voltage V
cap1
at the one end of the capacitor C
1
to amplify and output the difference thereof. Similarly, P-channel MOS transistors Qp
17
-Qp
19
and N-channel MOS transistors Qn
41
-Qn
43
constitute a second amplifier A
2
for comparing the reference voltage V
ref
and the voltage V
cap2
at the one end of the capacitor C
2
to amplify and output the difference thereof.
NAND gates G
1
and G
2
constitute an order logic circuit for outputting the order logic of the two amplifiers. In accordance with the output of the order logic circuit, the voltage level of the common gate of the transistor Qn
45
and the transistor Qp
20
and the voltage level of the common gate of the transistor Qn
46
and the transistor Qp
21
are alternately set at “H” (high level) and “L” (low level).
The operation of the oscillation circuit of
FIG. 2
will be described below.
In a stand-by state, the signal V
start
is set at “H”. In this time, the P-channel MOS transistors Qp
1
, Qp
14
, Qp
17
, and the N-channel MOS transistor Qn
40
and Qn
43
are turned off to shut the power supply system. While, the P-channel MOS transistor Qp
13
and the N-channel MOS transistors Qn
34
, Qn
35
, and Qn
36
are turned on, thereby the circuit is set at an initial state. In this time, the output from the NAND gate G
2
is set at “H” and the output from the NAND gate G
1
is set at “L”. In accordance with the outputs from the NAND gates, the voltage V
cap1
of the one end of the capacitor C
1
is set at “L”, and the voltage V
cap2
of the one end of the capacitor C
2
is set at “H”. The output VOSC of the oscillation circuit is thus set at “L”.
When the signal V
start
is turned from “H” to “L”, the oscillation starts: the P-channel MOS transistor Qp
13
and the N-channel MOS transistors Qn
34
, Qn
35
, and Qn
36
are turned off, in contrast, the P-channel MOS transistors Qp
1
, Qp
14
, Qp
17
, and the N-channel MOS transistors Qn
40
and Qn
43
are turned on. In this time, the reference current generating circuit and the differential amplifiers A
1
and A
2
are set in the active state.
In the oscillation starting state, V
cap1
is set at “L” with respect to V
ref
, and the differential amplifier A
1
operates to drop the voltage level of a node N
1
. The output of the NAND gate G
1
is thereby inverted to “H”. In contrast, V
cap2
is set at “H” with respect to V
ref
, and thus the other differential amplifier A
2
operates to increase the voltage level of a node N
2
to “H”, and the output of the NAND gate G
2
is inverted to “L” (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at “H”).
When the NAND gate G
1
outputs the signal at “H” level in the above-mentioned manner, the transistor Qn
46
is turned on, thereby the capacitor C
2
discharges the current I
ref
equal to the current flowing through the resistor R
1
of the reference current generating circuit. Thus, the voltage level V
cap2
is dropped to a level lower than V
ref
, and the potential level of the node N
2
is thus dropped to invert the output of the NAND gate G
2
to “H” (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at “L”). While, the NAND gate G
2
outputs “L” to turn on the transistor Qp
20
, and the capacitor C
1
is charged to the power supply voltage Vcc. The potential level V
cap1
of the capacitor C
1
is thus increased to increase the potential level of the node N
1
.
In this manner, the levels of G
1
and G
2
are stabilized at “H” and “L”, respectively, during a period from the time when V
cap2
is set at Vcc to the time when V
cap2
is dropped to V
ref
.
When the NAND gate G
2
outputs “H”, the transistor Qn
45
is turned on, and the capacitor C
1
discharges the current I
ref
equal to the current flowing through the resistor R
1
of the reference current generating circuit (in this time, the transistors Qn
2
, Qn
6
, and Qn
7
have substantially the same characteristics and size). The voltage level V
cap1
of the capacitor C
1
is dropped to a level lower than V
ref
, and the potential level of the node N
1
is dropped to invert the output of the NAND gate G
1
to “H” (in this time, the voltage level of the output signal VOSC of the oscillation circuit is set at “H”).
While, when the NAND gate G
1
outputs “L”, the transistor Qp
21
is turned on, and the capacitor C
2
is charged to the power supply voltage Vcc thereby. The potential level V
cap2
of the capacitor C
2
is thus increased to increase the potential level of the node N
2
. As described above, the levels of G
1
and G
2
are stabili
Kanda Kazushige
Nakamura Hiroshi
Banner & Witcoff LTD
Wells Kenneth B.
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