Static information storage and retrieval – Addressing – Sync/clocking
Patent
1996-09-16
1998-11-10
Le, Vu A.
Static information storage and retrieval
Addressing
Sync/clocking
36518901, 365191, G11C 700
Patent
active
058354450
ABSTRACT:
The present invention is a method and apparatus for reducing the effects of transmission line impedance on the clock signal in a semiconductor device. In a departure from the prior art, the present invention includes multiple clock inputs, located near the device's synchronous input/output ports, reducing the maximum distance that any single internal clock signal must travel and thereby reducing the amount of delay caused by the effects of transmission line impedance on the internal clock signals. The present invention also includes a read only memory ("ROM") to improve the speed of the device and to provide additional space in the highly congested areas between the column decoder and address ports of the device. The ROM is programmed to decipher row address for information that would be beneficial in a redundant column access.
REFERENCES:
patent: 5327390 (1994-07-01), Takasugi
patent: 5384737 (1995-01-01), Childs et al.
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5426333 (1995-06-01), Maeda
patent: 5535171 (1996-07-01), Kim et al.
patent: 5652724 (1997-07-01), Manning
Hitachi, HM5216800 Series, HM5416800 Series, Jan. 18, 1993.
Motorola Inc., Memories, 1991, pp. 7-32 through 7-36 and 7-100 through 7-107.
Hitachi , Ltd.
Le Vu A.
LandOfFree
Semiconductor integrated circuit device having a synchronous out does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device having a synchronous out, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device having a synchronous out will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1524248