Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1992-05-29
1993-05-04
Dixon, Joseph L.
Static information storage and retrieval
Addressing
Plural blocks or banks
365 51, 365 63, 257784, 257786, G11C 506
Patent
active
052087824
ABSTRACT:
A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.
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Hori Ryoichi
Ishihara Masamichi
Iwai Hidetoshi
Kasama Yasuhiro
Maeda Toshio
Dixon Joseph L.
Hitachi , Ltd.
Hitachi VLSI Engineering Corp.
Lane Jack A.
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