Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-04-27
2002-12-03
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S348000, C257S359000, C257S797000
Reexamination Certificate
active
06489662
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor integrated circuit formed on an SOI substrate.
2. Description of the Related Art
A semiconductor integrated circuit formed on an SOI substrate is widely known at present. In particular, a high speed MOS transistor has excellent characteristics by utilizing a complete depleting mode in comparison with a MOS transistor formed on a conventional silicon substrate.
In contrast to this, there is known a laser trimming method for adjusting analog characteristics in a device of an analog semiconductor integrated circuit. For example, the laser trimming method is described in Japanese Patent Application Laid-open No. Hei 5-13670. In this method, after integrated circuits are two-dimensionally patterned in a semiconductor wafer, electric characteristics of each integrated circuit are measured in a wafer state. Next, a fuse element arranged in one portion of wiring is selected to adjust the analog characteristics and is cut by irradiating a laser beam. The analog characteristics of the integrated circuit can be matched with desired characteristics by selectively cutting the fuse element by such a laser trimming method. A pattern for positioning is arranged on a semiconductor wafer surface to irradiate the laser beam to a predetermined fuse element.
FIG. 2A
is a plan view of a conventional positioning pattern.
FIG. 2B
is a cross-sectional view of the conventional positioning pattern.
FIG. 2C
is a graph showing a change in light reflection amount when this pattern for positioning is scanned along the direction of the line B-B′ by the irradiation of the light beam. In the conventional positioning pattern, an outer circumferential portion is composed of a first insulating film
102
formed of a silicon oxide film arranged on a silicon substrate
101
and, a second insulating film
104
formed of a PSG film, etc., and an aluminum film
105
is arranged inside this outer circumferential portion. When the light beam is scanned along a B-direction of
FIG. 2A
, a light reflecting pattern is obtained as shown in
FIG. 2C
since reflectivity of the aluminum film
105
is high. A position relation between the positioning pattern and the fuse element formed of a polycrystal silicon film of the integrated circuit is determined at the time of designing. Accordingly, the coordinates of a desired fuse element are calculated by detecting the positioning pattern by the irradiation of the light beam, and the fuse element can be selectively trimmed by irradiating the laser beam at this coordinate place.
However, when a complete depleting mode, in particular, is used in the semiconductor integrated circuit formed on the conventional SOI substrate, the thickness of a monocrystal silicon device forming layer formed on the SOI substrate through a buried oxide film must be set to about 1000 angstroms or less. Accordingly, it is difficult to form a high withstand voltage series element and an ESD protecting element for preventing ESD breakdown (electrostatic breakdown) in the thin monocrystal silicon device forming layer.
Further, no scribe is considered in the semiconductor integrated circuit formed on the conventional SOI substrate. Accordingly, there is a case in which inconveniences such as cracking, breakage, etc., are caused in a dicing process for cutting-out an IC chip.
It is not limited to the IC formed on the SOI substrate but is a general knowledge to form a fuse element of a polycrystal silicon film. However, in the laser trimming, no accurate positioning operation can be performed since the fuse element and the positioning pattern are formed of different thin films. Namely, when the pattern for positioning is detected by a pattern of aluminum and the polycrystal silicon film as the fuse element is laser-trimmed, the position of a laser irradiated region
32
is shifted from the fuse element
31
as shown in FIG.
8
. Since an energy distribution in the laser irradiated region
32
corresponds to a Gaussian distribution, an energy intensity is high in a peak portion of a laser
80
but energy intensity in a laser irradiating end portion is low. Accordingly, when there is a large shift in alignment between patterning of the polycrystal silicon film and patterning of the aluminum film in a wafer process, a problem exists in that no fuse element can be stably cut. Reference numerals
33
and
34
respectively designate a burnt portion of a base and a portion left in the fuse cut.
Further, in an analog IC such as a voltage detector, a breeder resistor formed of a plurality of polycrystal silicon resistors is used in many cases. However, it is difficult to obtain the same resistance value in the polycrystal silicon resistors due to an influence of grain. Accordingly, this difficulty has been a serious problem in the manufacture of the analog IC of having high accuracy.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor device in which an analog IC of high accuracy which mixedly has a high speed MOS transistor of a complete depletion type and a high withstand voltage type MOS transistor is formed on an SOI substrate, so that the semiconductor device is strong against ESD breakdown and cracking, breakage, etc., are prevented in a dicing process.
Further, another object of the present invention is to make a fuse element region compact and reduce cost by improving a positioning accuracy of trimming.
To attain the above objects, the present invention has the following structure.
(1) A semiconductor device in which a fuse element for laser trimming, a pattern for laser trimming positioning, a high speed MOS transistor of a complete depletion type, a high withstand voltage type MOS transistor, an ESD protecting element and a bleeder resistor formed of a plurality of resistors are formed in a semiconductor integrated circuit formed on an SOI substrate.
(2) The semiconductor device as described in the above item (1), in which the pattern for laser trimming positioning is composed of a high light reflectivity region and a low light reflectivity region, the high light reflectivity region being formed of a high light reflectivity film formed on a flat base, the low light reflectivity region being formed of the high light reflectivity film formed on a grid, stripe or dot pattern that is for causing diffused reflection of light and is formed of the same thin film as the fuse element for laser trimming.
(3) The semiconductor device as described in the above item (1), in which the fuse element for laser trimming is formed of a monocrystal silicon device forming layer on the SOI substrate.
(4) The semiconductor device as described in the above item (1), in which the high speed MOS transistor of a complete depletion type is formed in the monocrystal silicon device forming layer, and the high withstand voltage type MOS transistor and the ESD protecting element are formed on a silicon substrate from which the monocrystal silicon device forming layer on the SOI substrate and a buried oxide film are removed.
(5) The semiconductor device as described in the above item (1), in which the bleeder resistor is formed of a monocrystal silicon device forming layer.
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Adams & Wilks
Eckert II George C.
Seiko Instruments Inc.
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