Semiconductor integrated circuit device formed by automatic...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays

Reexamination Certificate

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Details

C257S202000, C257S204000, C257S206000, C257S207000, C257S210000, C257S909000, C438S128000, C438S587000, C438S598000

Reexamination Certificate

active

07368767

ABSTRACT:
A standard cell is read from a library and automatic layout wiring is performed, thereby configuring a circuit. Next, each cell column in the configured circuit is searched for an empty region. In the empty region in the cell column searched for, a spacer cell or a filler cell is placed. At this time, using the spacer cell or filler cell, the well potential of the standard cells in the cell column is fixed.

REFERENCES:
patent: 5764533 (1998-06-01), deDood
patent: 2000-332118 (2000-11-01), None
patent: 2003-133416 (2003-05-01), None

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