Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-12-16
2002-01-08
Wilczewski, M (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S754000, C257S296000, C257S306000, C438S477000, C438S910000
Reexamination Certificate
active
06337514
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a non-permeable layer for a chemical species against the surface state and a process for fabricating the semiconductor integrated circuit device.
DESCRIPTION OF THE RELATED ART
A typical example of the semiconductor dynamic random access memory device is illustrated in
FIGS. 1 and 2
. The prior art semiconductor dynamic random access memory device is disclosed in IEDM, 1988, pages 596 to 599.
The prior art semiconductor dynamic random access memory device is fabricated on a p-type silicon substrate
1
. A field oxide layer
2
is selectively grown on the major surface of the p-type silicon substrate
1
, and defines plural active regions
3
a
/
3
b
. The active regions
3
a
decline toward the left side, and are arranged at intervals. On the other hand, the active regions
3
b
decline toward the right side, and are also arranged at intervals. The right end portions of the active regions
3
a
are alternated with the left end portions of the active regions
3
b
. Thus, the active regions
3
a
and the active regions
3
b
are arranged on the major surface of the p-type silicon substrate in a staggered manner. The active regions
3
a
/
3
b
form a memory cell array, and the prior art semiconductor dynamic random access memory device includes plural memory cell arrays.
Each of the active regions
3
a
/
3
b
is assigned to a pair of memory cells, and the memory cell is implemented by a series combination of an n-channel enhancement type access transistor and a storage capacitor. Arsenic is selectively ion implanted into each active region
3
a
/
3
b
, and two source regions
4
a
and a common drain region
4
b
are formed in each active region
3
a
/
3
b
. The source regions
4
a
and the common drain region
4
b
are indicated by hatching lines so as to be easily discriminated from other components.
The surface portion between the source region
4
a
and the common drain region
4
b
serves as a channel region, and the channel region is covered with a silicon oxide layer. The silicon oxide layer serves as a gate insulating layer of the n-channel enhancement type access transistor, and word lines
5
extend over the gate insulating layers and the field oxide layer therebetween.
The word lines
5
are covered with a first inter-level insulating layer
6
, and bit contact holes
7
are formed in the first inter-level insulating layer
6
. The common drain regions
4
a
are exposed to the bit contact holes
7
. The locations of the bit contact holes
7
are represented by oblique lines inserted in boxes in FIG.
1
. Bit lines
8
are patterned on the first inter-level insulating layer
6
, and are held in contact with the common drain regions
4
b
through the bit contact holes
7
.
The bit lines
8
are covered with a second inter-level insulating layer
9
, and node contact holes
10
penetrate through the second inter-level insulating layer
9
and the first inter-level insulating layer
6
. The node contact holes
10
are open to the source regions
4
a
, respectively. The locations of the node contact holes
10
are indicated by “X” inserted in boxes in FIG.
1
.
Storage electrodes
11
are formed on the second inter-level insulating layer
9
, and are held in contact with the source regions
4
a
through the node contact holes
10
, respectively. The surfaces of the storage electrodes
11
are covered with a dielectric layer
12
, and a cell plate electrode
13
is opposed to the storage electrodes
11
through the dielectric layer
12
. The cell plate electrode
13
is covered with a third inter-level insulating layer
14
, and the third inter-level insulating layer
14
is removed from the layout shown in FIG.
1
.
A central area of the major surface is assigned to the memory cell arrays, and peripheral circuits such as decoders and sense amplifiers are assigned a peripheral area around the central area. The cell plate electrode
13
is shared between the memory cells, and occupies over the central area. The cell plate electrode
13
may be separated into cell plate sub-electrodes, which are respectively associated with the memory cell arrays.
The manufacturer has been increasing the memory capacity of the semiconductor dynamic random access memory device, and, accordingly, the cell plate electrode is enlarged. In other words, the cell plate electrode covers the wide central region of the p-type silicon substrate
1
.
The n-channel enhancement type access transistors are respectively incorporated in the memory cells of the prior art semiconductor dynamic random access memory device, and the manufacturer is required to decrease the density of surface state during the manufacturing process. The manufacturer carries out a hydrogen annealing after the patterning step for forming the cell plate electrode
13
for decreasing the density of surface state. The hydrogen atoms are coupled with the dangling bonds at the interface between the channel regions and the gate insulating layers, and decreases the density of the surface state.
As described hereinbefore, the wide cell plate electrode
13
covers the central region of the p-type silicon substrate
1
, and does not allow the hydrogen atoms to pass therethrough. The cell plate electrode is not a problem in the semiconductor dynamic random access memory device in the previous generations. The central region assigned to the memory cell arrays is not so wide that the hydrogen atoms are diffused from the exposed surface of the semiconductor structure to the channel regions. If the manufacturer carries out the hydrogen annealing before the deposition of polysilicon for the cell plate electrode, the hydrogen surely reaches the boundaries, and decreases the surface state. However, the hydrogen is released from the dangling bonds during a heat treatment after the annealing. For this reason, the hydrogen annealing is carried out after the patterning step for the cell plate electrode.
The decrease of surface state is required for the field effect transistors incorporated in any kind of semiconductor integrated circuit device, and a non-permeable layer like the cell plate electrode is sometimes incorporated in the semiconductor integrated circuit device.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a semiconductor integrated circuit device, which allows a chemical species against the surface state to reach a boundary where surface states take place.
It is also an important object of the present invention to provide a process for fabricating the semiconductor integrated circuit device.
The present inventor contemplated the problem, and supposed that the hydrogen atoms would pass a window formed in the cell plate electrode. The present inventor investigated a cell plate electrode formed with a window or the like. The present inventor found a cell plate electrode divided into plural pieces, and the prior art semiconductor dynamic random access memory device with the plural cell plate sub-electrodes was disclosed in Japanese Patent Publication of Unexamined Application No. 3-102870. The purpose of the cell plate electrode divided into the sub-electrodes was reduction of electric charge accumulated therein during a plasma etching for patterning a polysilicon layer into the cell plate electrode. The Fowler-Nordheim tunneling current flew through a dielectric layer thinner than the others due to the accumulated electric charge, and was causative of the time-dependent dielectric breakdown of the thin dielectric layers of the storage capacitors. The amount of the Fowler-Nordheim tunneling current was proportional to the area of the cell plate electrode, and the above-mentioned Japanese Patent Publication of Unexamined Application proposed to divide the cell plate electrode into the plural sub-electrodes. The narrow sub-electrodes reduced the amount of Fowler-Nordheim tunneling current, and prevented the dielectric layers from the tim
NEC Corporation
Wilczewski M
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