Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-01-16
2002-07-23
Berhane, Adolf Deneke (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06424134
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a configuration of an internal voltage generation circuit for internally generating an internal voltage used in a semiconductor device such as a semiconductor integrated circuit device. More particularly, the present invention relates to a semiconductor device including a reference voltage generation circuit for generating a reference voltage independent of an external power supply voltage and an internal voltage generation circuit for generating an internal voltage at a necessary level in accordance with the reference voltage.
2. Description of the Background Art
In semiconductor integrated circuit devices, a reference voltage generation circuit generating a reference voltage for setting a level of an internal voltage has been employed in many cases, in order to convert a level of an externally applied voltage to generate the internal voltage of a desired level. The reference voltage generation circuit can maintain a level of a reference voltage at a constant level without being affected by variation in an external power supply voltage and therefore, a level of an internal voltage set in accordance with the reference voltage can be kept constant to operate internal circuitry in a stable manner.
FIG. 16
is a block diagram schematically showing a configuration of a reference voltage generation section in a conventional semiconductor integrated circuit device. In
FIG. 16
, DRAM (dynamic random access memory) is shown as a typical semiconductor integrated circuit device. As shown in
FIG. 16
, a reference voltage generating circuitry includes: a constant current generation circuit
900
generating a constant current Icst; and reference voltage generation circuits
902
,
904
,
906
and
908
, connected to the constant current generation circuit
900
, performing current/voltage conversion on the constant current Icst to generate reference voltages Vrefs, Vrefi, Vrefd and Vrefb, respectively. Internal voltages used in the DRAM are generated in accordance with the reference voltages Vrefs, Vrefi, Vrefd and Vrefb.
An internal voltage generation circuitry further includes: a voltage down converter
910
generating an array power supply voltage Vdds supplied to an array circuit
920
in accordance with the reference voltage Vrefs; a voltage down converter
912
generating a periphery power supply voltage Vddi supplied to a peripheral circuit
922
in accordance with the reference voltage Vrefi; a boosted voltage generation circuit
914
generating a boosted voltage Vpp in accordance with the reference voltage Vrefd; and a boosted voltage generation circuit
916
generating a boosted voltage Vddb in accordance with the reference voltage Vrefb.
The boosted voltage generation circuit
914
is provided with: a voltage divider circuit
911
dividing the boosted voltage Vpp generated by the boosted voltage generation circuit
914
; and a detection circuit
913
comparing an output voltage of the voltage divider circuit
911
with the reference voltage Vrefb to control a voltage boosting operation of the boosted voltage generation circuit
914
in accordance with the comparison result. The boosted voltage Vpp from the boosted voltage generation circuit
914
is supplied to, for example, a boosted voltage utilizing circuit
924
such as a word line drive circuit.
The boosted voltage generation circuit
916
is provided with: a voltage divider circuit
915
voltage-dividing the boosted voltage Vddb; and a detection circuit
917
comparing an output voltage of the voltage divider circuit
915
with the reference voltage Vrefb to activate/deactivate a voltage boosting operation of the boosted voltage generation circuit
916
in accordance with the comparison result. The boosted voltage Vddb is supplied to a boosted voltage utilizing circuit
926
including, for example, a bit line isolation instructing signal generation circuit, a bit line equalize signal generation circuit and others.
The array circuit
920
includes, for example, a memory cell array; a sense amplifier circuit performing sensing and amplification of data of memory cells. The peripheral circuit
922
includes a control circuit generating an internal operation control signal and others.
Levels of the power supply voltages Vdds and Vddi generated by voltage down converters
910
and
912
are determined in accordance with the reference voltages Vrefs and Vrefi, respectively. Likewise, levels of boosted voltages Vpp and Vddb are determined by voltage-division ratios of the voltage divider circuits
911
and
915
and levels of the reference voltages Vrefd and Vrefb. Therefore, the voltage down converters
910
and
912
and the boosted voltage generation circuits
914
and
916
are required to generate the voltages Vdds, Vddi, Vpp and Vddb in a stable manner in order to operate the circuits
920
,
922
,
924
and
926
in a stable manner. That is, since levels of these voltages are determined by the reference voltages, the reference voltage generation circuits
902
,
904
,
906
and
908
have to generate the reference voltages Vrefs, Vrefi, Vrefd and Vrefb in a stable manner. Especially, it is very important to generate the reference voltages Vrefs, Vrefi, Vrefd and Vrefb with high precision since operating characteristics of internal circuits such as the array circuit
920
are determined by levels of the voltages Vdds, Vddi, Vpp and Vddb.
FIG. 17
is a graph showing a characteristic of a reference voltage. In
FIG. 17
, one of the reference voltages Vrefs, Vrefi, Vrefd and Vrefb shown in
FIG. 16
is represented as a reference voltage Vref. As an externally applied voltage (external power supply voltage) rises, a constant current Icst from the constant current generation circuit
900
increases, and the reference voltage Vref rises with rise in the externally applied voltage (external power supply voltage). The region in which a voltage level of the reference voltage Vref rises is called a linear region.
When the externally applied voltage (external power supply voltage) reaches a certain voltage level, the constant current Icst from the constant current generation circuit
900
shown in
FIG. 16
becomes constant and in response, the reference voltage Vref is made constant as well. Accordingly, when the externally applied voltage increases beyond the certain voltage value, a level of the reference voltage Vref is kept at a constant value independent of a level of the externally applied voltage (external power supply voltage). The region in which the reference voltage Vref is at a constant level is called a flat region.
Internal circuitry such as the array circuit is operated in the flat region in which the reference voltage Vref is constant. Thus, a reference voltage is generated stably independently of variations in the externally applied voltage (external power source voltage), thereby enabling generation of a stable internal voltage.
FIG. 18
is a block diagram schematically showing a configuration of a reference voltage generating circuit shown in FIG.
16
. The reference voltage generation circuits
902
,
904
,
906
and
908
have substantially the same configurations as one another, except for that levels of the reference voltages generated by these circuits are different from one another. In
FIG. 18
, the reference voltage generation circuit
930
is shown representably.
As shown in
FIG. 18
, the reference voltage generation circuit
930
includes: a current source
930
a
for generating a constant current corresponding to the constant current Icst from the constant current generating circuit
900
; a trimmable impedance element
930
b
for converting the constant current Icst from the current source
930
a
to a voltage level; and a tuning mechanism
930
c
for adjusting an impedance value of the trimmable impedance element
930
b
. A stabilization capacitance
930
d
for stabilizing the reference voltage Vref is provided at an output node
930
f
of the reference voltage generation circuit
930
.
In the reference voltage g
Akiyama Mihoko
Fujii Nobuyuki
Kobayashi Mako
Morishita Fukashi
Taito Yasuhiko
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