Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Measuring or testing
Reexamination Certificate
2000-02-29
2001-12-11
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Measuring or testing
C324S527000
Reexamination Certificate
active
06330297
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device capable of reading out chip-specific information during testing and evaluation.
2. Description of the Related Art
With advances in semiconductor manufacturing technology, the miniaturization of semiconductor integrated circuit devices has been advancing and their packing density increasing in recent years and, with this trend, it is required to reduce the chip area. To achieve this, there is a need to reduce as much as possible the long wiring used only for the testing and evaluation of the chip (the wiring is long compared with the chip internal wiring).
It is known in the prior art to provide a semiconductor integrated circuit device (chip) in which information specific to the chip is written using fuses or the like, allowing the information to be read out when testing and evaluating the chip. More specifically, in the prior art semiconductor integrated circuit device, the lot number, wafer number, chip number (code), etc. specific to the chip are written using fuses or the like, and binary data is input from the outside and compared with the internally stored binary data for verification of the chip-specific data such as the code.
The chip-specific lot number, wafer number, etc. are used, for example, to identify the lot, wafer, etc. associated with a defective chip discovered during testing, track down the semiconductor process that caused the defective chip, and so on.
The prior art and its associated problem will be described later, in detail, with reference to the accompanying drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit device that permits a reduction in layout area and facilitates efficient layout work, by reducing the number of wiring lines formed from pads to a signature circuit (comparison/verification circuit).
According to the present invention, there is provided a semiconductor integrated circuit device comprising a data holding section for storing information; a counter for counting the number of externally applied pulses; and a comparison/verification section for comparing an output of the counter with an output of the data holding section, and for verifying whether the outputs match or not.
The data holding section may store the information by opening or not opening a fuse. The data holding section may store the information by using a ROM. The information stored in the data holding section may be information specific to the semiconductor integrated circuit device. The information specific to the semiconductor integrated circuit device may include a lot number, a wafer number, or a chip number.
An output of the comparison/verification section may be extracted from the semiconductor integrated circuit device according to whether or not a current flows to a designated pin. The information stored in the data holding section may be read out when testing and evaluating the semiconductor integrated circuit device. The semiconductor integrated circuit device may be a synchronous dynamic random access memory.
REFERENCES:
patent: 4276468 (1981-06-01), Nagamoto et al.
patent: 4517684 (1985-05-01), Fennel
patent: 5467304 (1995-11-01), Uchida et al.
Kano Hideki
Saitoh Satoru
Yamada Shin-ichi
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Lam Tuan T.
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