Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-02-13
2002-01-15
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S540000, C327S407000
Reexamination Certificate
active
06339357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a semiconductor integrated circuit device having at least a test mode for externally monitoring an internal voltage. Specifically, this invention relates to a semiconductor integrated circuit device having an internal power supply voltage generating circuit for generating an internal power supply voltage according to a reference voltage, and more specifically to a configuration permitting externally monitoring or externally changing the reference voltage.
2. Description of the Background Art
Now, as an example of the semiconductor integrated circuit device, a semiconductor memory device is considered. The semiconductor memory device has been made with higher integration and higher density to obtain an increased storage capacity, and accordingly, the elements or the components of the device have been miniaturized. To ensure the reliability of these miniaturized elements such as a MOS transistor (insulated gate type field effect transistor), the operating power supply voltage should be made low. Such a lowering of the operating power supply voltage can reduce the power dissipation which is proportional to the square of the operating power supply voltage. External logics and processors, however, have not been miniaturized to the degree of the semiconductor memory device. Therefore, the power supply voltage for those devices cannot be made as low as that for the semiconductor memory device, because their high-speed operation will not be ensured. In addition, the miniaturized memory devices must retain compatibility with previous-generation semiconductor memory devices.
Therefore, the power supply voltage provided from an outside of the semiconductor memory device, such as a system power supply voltage, is down converted within the device to generate an internal power supply voltage at a required voltage level.
FIG. 19
is a diagram showing an example of the configuration of a conventional internal power supply circuit. Referring to
FIG. 19
, the internal power supply circuit includes a reference voltage generating circuit RFG which generates reference voltage Vref at a prescribed voltage level, and an internal voltage down converter VDC which compares reference voltage Vref from the reference voltage generating circuit RFG with the voltage on an internal power supply line IVL, and according to the result of comparison, supplies current from an external power supply node EX onto internal power supply line IVL to adjust the voltage level on the internal power supply line IVL to generate an internal power supply voltage intVcc.
The internal voltage down converter VDC includes a comparator CMP for comparing reference voltage Vref with internal power supply voltage intVcc on internal power supply line IVL, and a drive transistor DR formed of a p channel MOS transistor and for supplying current from external power supply node EX onto internal power supply line IVL according to the output signal from the comparator CMP. Comparator CMP has a positive input receiving internal power supply voltage intvcc on internal power supply line IVL and a negative input receiving reference voltage Vref.
When internal power supply voltage intvcc is higher than reference voltage Vref, the internal voltage down converter VDC pulls up the output signal from comparator CMP to a high level for rendering drive transistor DR nonconductive to stop current supply from external power supply node EX to internal power supply line IVL. On the other hand, if internal power supply voltage intvcc on internal power supply line IVL is lower than reference voltage Vref, the comparator CMP outputs a signal at a low level, increasing the conductance of drive transistor DR, and thus the current in proportion to the difference between the internal power supply voltage intVcc and the reference voltage Vref from external power supply node EX is supplied to internal power supply line IVL through drive transistor DR. As a result, the voltage level of internal power supply voltage intvcc is maintained substantially at the same level as reference voltage Vref.
FIG. 20
is a diagram showing an example of the configuration of reference voltage generating circuit RFG shown in
FIG. 19
, which is described, for example, in Japanese Patent Laying-Open No. 7-37381.
Referring to
FIG. 20
, the reference voltage generating circuit RFG includes: a p channel MOS transistor P
1
connected between external power supply node EX and a node M
1
and having a gate receiving a ground voltage; an n channel MOS transistor N
1
connected between node M
1
and a ground node and having its gate connected to node M
1
; a p channel MOS transistor P
2
connected between external power supply node EX and a node M
2
and having its gate connected to node M
2
; an n channel MOS transistor N
2
connected between node M
2
and a ground node and having its gate connected to node M
1
; a p channel MOS transistor P
3
connected between external power supply node EX and a node M
4
and having its gate connected to node M
2
; a p channel MOS transistor P
4
connected between node M
4
and node M
3
and having its gate connected to node M
3
; and an n channel MOS transistor N
3
connected between node M
3
and a ground node and having its gate connected to node M
1
.
The two p channel MOS transistors P
2
and P
3
constitute a current mirror circuit, and their size ratio (size being a ratio of gate width to gate length) is set to 1:1. Meanwhile, each of the n channel MOS transistors N
2
and N
3
constitutes a current mirror circuit with n channel MOS transistor N
1
. The gate width to gate length ratio of n channel MOS transistor N
2
is set to one half (½) that of n channel MOS transistor N
3
.
The reference voltage generating circuit RFG further includes a p channel MOS transistor P
5
connected between external power supply node EX and node M
3
and having its gate connected to node M
3
, a p channel MOS transistor P
6
connected between external power supply node EX and a node M
5
and having its gate connected to node M
4
, and diode-connected p channel MOS transistors P
7
, P
8
and P
9
connected in series to one another between node M
5
and a ground node.
The absolute value of threshold voltage of p channel MOS transistor P
5
is set higher than that of p channel MOS transistor P
4
. The ratio of gate width to gate length of p channel MOS transistor P
6
is set at the same value as that of each of p channel MOS transistors P
7
-P
9
. Now, the operation of reference voltage generating circuit RFG shown in
FIG. 20
will be described in brief.
P channel MOS transistor P
1
having its gate connected to the ground node serves as a current source and generates a reference current, which in turn is supplied to n channel MOS transistor N
1
. N channel MOS transistors N
1
and N
2
constituting a current mirror circuit have the same size with each other, so that current flowing through n channel MOS transistor N
2
is the same in amount as the current flowing through n channel MOS transistor N
1
. N channel MOS transistor N
2
is supplied with current from p channel MOS transistor P
2
, and the mirror current of the current flowing through p channel MOS transistor P
2
flows through p channel MOS transistor P
3
. As p channel MOS transistors P
2
and P
3
have the same size with each other, the same amount of current flows therethrough. The current i from p channel MOS transistor P
3
flows through p channel MOS transistor P
4
and n channel MOS transistor N
3
to the ground node.
The ratio of gate width to gate length of n channel MOS transistor N
3
is set twice that of n channel MOS transistor N
2
, and thus the current 2i, twice the magnitude of current i flowing through p channel MOS transistors P
3
and P
4
, flows through n channel MOS transistor N
3
. The remaining current i is supplied from p channel MOS transistor P
5
to n channel MOS transistor N
3
. The absolute value of threshold voltage of p cha
Itou Takashi
Yamasaki Kyoji
Callahan Timothy P.
Nguyen Hai L.
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