Semiconductor integrated circuit device and wiring method thereo

Details Semiconductor integrated circuit device and wiring method thereo Semiconductor integrated circuit device and wiring method thereo

1988-11-23

1992-01-21

Hille, Rolf

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 68, 357 40, 357 71, 307443, 307465, 307468, H01L 2710, H01L 2715, H01L 2348

Patent

active

050831810

ABSTRACT:
In a gate array including a plurality of output buffer circuits whose output levels change simultaneously with one another, a power source voltage or a reference voltage is supplied to the plurality of output buffer circuits whose output levels change simultaneously with one another by the same and exclusive power source voltage wiring or reference voltage wiring and is separated from power source voltage wirings or reference voltage wirings connected to other output buffer circuits and this wiring design is made by DA (Design Automation) combining fixed patterns with connection patterns. This designing method can prevent any adverse influences of the operations of the output buffer circuits whose output levels change simultaneously with one another on the other output buffer circuits and on input buffer circuits.

REFERENCES:
patent: 4591894 (1986-05-01), Kawakami
patent: 4656370 (1987-04-01), Kanuma
patent: 4857765 (1989-08-01), Cahill et al.
Itoh et al., "Array and Gb Logic", 2/11/82, pp. 176 abd 177, Digest of Technical Papers.

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