Semiconductor integrated circuit device and semiconductor...

Details Semiconductor integrated circuit device and semiconductor... Semiconductor integrated circuit device and semiconductor...

2002-06-19

2003-07-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S226000, C365S233100

Reexamination Certificate

active

06594170

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-185284, filed Jun. 19, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device and semiconductor device system and, more particularly to a synchronous semiconductor IC device and semiconductor device system.
2. Description of the Related Art
Presently, there has been widely used such a semiconductor memory for inputting/outputting data in synchronization with an external clock signal as synchronous DRAM (SDRAM), a double data-rate synchronous DRAM (DDR-SDRAM) and a ram-bus DRAM (RDRAM).
Of these, a DDR-SDRAM use an external reference potential VREF to decide a HIGH/LOW logical level of an external pin such as a data external pin.
FIG. 1
is a block diagram for outlining a semiconductor device system in which such a synchronous semiconductor memory is incorporated and
FIG. 2
, an expanded view for showing a frame A surrounded by a broken line in FIG,
1
.
As shown in
FIG. 1
, on a wiring board are arranged as external wiring lines an external signal line (DQ) through which are propagated external signals (external input signal DIN and external output signal DOUT in this specification), an external reference potential line (VREF) to which is applied the external reference potential used in decision of the logical level of the external input signal DIN, an external input control clock signal line (CLOCK
1
) through which is propagated an external input control clock signal CLOCK
1
, and an external output control clock signal line (CLOCK
2
) through which is propagated another external output control clock signal CLOCK
2
. To the wiring board
101
is electrically connected a synchronous semiconductor memory
102
.
The synchronous semiconductor memory
102
is provided with external pins
103
, to which the wiring lines arranged on the wiring board
101
are connected. These external pins
103
are electrically connected via a pad
104
to internal wiring lines arranged in the synchronous semiconductor memory
102
. In the example shown in
FIGS. 1 and 2
, those wiring lines connected to the external wiring lines include an internal reference potential line (Vref) electrically connected to the external reference potential line (VREF), an internal input control clock signal line (clock
1
) electrically connected to the external input control clock signal line (CLOCK
1
), and an internal output control clock signal line (clock
2
) electrically connected to the external output control clock signal line (CLOCK
2
).
Next, the following will describe operations of these lines.
<Operations When Inputting Signal>
The signal is input in synchronization with at least one of leading and trailing edges of the internal input control clock signal clock
1
synchronized with the external input control clock signal CLOCK
1
.
Specifically, an input circuit
105
receives an external input signal DIN through the pad
104
as an internal input signal Din. Then, it decides the logical level of this internal input signal Din against the internal reference potential Vref.
The logical level is specifically decided by an input receiver (IN.R.)
106
of the input circuit
102
. The input receiver
106
compares, for example, the potential of the internal input signal Din to that of the internal reference potential Vref. If the potential of the internal input signal Din is lower than the internal reference potential Vref, it decides that the logical level is “LOW” and, if it is lower than that, decides that the logical level is “HIGH”.
The input receiver
106
is controlled by an input receiver control circuit (IN.C.)
107
. The input receiver control circuit
107
generates an input control signal synchronized with this internal input control clock signal clock
1
based on the internal input control clock
1
synchronized with the external input control clock signal CLOCK
1
. The input receiver
106
takes in the internal input signal Din in response to the input control signal to then output this internal input signal Din to the inside of the synchronous semiconductor memory
102
.
<Operations When Outputting Signal>
As in the case of signal inputting, the signal is output in synchronization with at least the leading and trailing edges of the internal output control clock clock
2
synchronized with the external output control clock CLOCK
2
.
Specifically, an output circuit
108
is comprised of an output driver (OUT.D.)
109
and an output driver control circuit (OUT.C.)
110
. An internal output signal Dout output from the inside of the synchronous semiconductor memory
102
is input to the output driver
109
.
The output driver
109
is controlled by the output driver control circuit (OUT.C.)
110
. The output receiver control circuit
110
generates an output control signal synchronized with the internal output control clock signal clock
2
based on the internal output control clock signal clock
2
synchronized with the external output control clock signal CLOCK
2
. The output driver
109
outputs the internal output signal Dout in synchronization with the output control signal to thereby drive the external signal line DQ via the pad
104
and the external pins
103
. Thus, an external output signal DOUT is propagated to the external signal line DQ.
It is here assumed that noise occurred in such a synchronous semiconductor memory
102
and had an influence on the internal input control clock signal clock
1
, the internal output control clock signal clock
2
, and the internal reference potential Vref. In this case, the following situation is expected.
<When Internal Input Control Clock Signal Clock
1
is Affected by Noise>
As shown in
FIGS. 3A and 3B
, if the internal input control clock signal clock
1
is affected by noise, for example, it is shifted in phase with respect to the external input control clock signal CLOCK
1
. This causes in turn the timing for taking in a signal by the input circuit
105
to be shifted from the edge of the external input control clock signal CLOCK
1
. This results in a change in a set-up time tS and a hold time tH of the input circuit
105
. If the set-up time tS and the hold time tH change, it is difficult for the input circuit
105
to take in the signal.
<When Internal Output Control Clock Signal Clock
2
is Affected by Noise>
As shown in
FIGS. 4A and 4B
, if the internal output control clock signal clock
2
is affected by noise, as in the case of the above-mentioned clock signal clock
1
, for example, the clock signal clock
2
is shifted in phase with respect to the external output control clock signal CLOCK
2
. This causes in turn the timing for outputting a signal by the output circuit
108
to be shifted from the edge of the external output control clock signal CLOCK
2
. As a result, the timing for propagating the external output signal DOUT through the external signal line DQ is shifted from the edge of the external output control clock signal CLOCK
2
, thus resulting in a change in an output time tQ. If the output time tQ changes, for example, it is difficult for a memory controller, not shown, to take in the external output signal DOUT.
<When Internal Reference Potential Vref is Affected by Noise>
As shown in
FIGS. 5A and 5B
, if the internal reference potential Vref is affected by noise, its potential fluctuates. If the internal reference potential Vref fluctuates, a difference in potential between itself and the “LOW” or “HIGH” level of an input signal decreases. Originally the internal reference potential Vref is set at an intermediate position between the “LOW” and “HIGH” levels. As such, if the potential difference between the internal reference potential Vref and the “LOW” or “HIGH” level is decreased, it is difficult for the input receiver
106
to decide the logical level.
Presently, to guard against these problem

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