Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2007-07-16
2008-11-25
Lee, Calvin (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S238000
Reexamination Certificate
active
07456486
ABSTRACT:
A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
REFERENCES:
patent: 4803534 (1989-02-01), Koike et al.
patent: 4873204 (1989-10-01), Wong et al.
patent: 5051958 (1991-09-01), Arakawa
patent: 5098854 (1992-03-01), Kapoor et al.
patent: 5121186 (1992-06-01), Wong et al.
patent: 5187122 (1993-02-01), Bonis
patent: 5194749 (1993-03-01), Meguro et al.
patent: 5406107 (1995-04-01), Yamaguchi
patent: 5462894 (1995-10-01), Spinner et al.
patent: 5483083 (1996-01-01), Meguro et al.
patent: 5523598 (1996-06-01), Watanabe et al.
patent: 5656524 (1997-08-01), Eklund et al.
patent: 5716871 (1998-02-01), Yamazaki et al.
patent: 5736421 (1998-04-01), Shimomura et al.
patent: 5834851 (1998-11-01), Ikeda et al.
patent: 5946565 (1999-08-01), Ikeda et al.
patent: 6548885 (2003-04-01), Ikeda et al.
patent: 7049680 (2006-05-01), Ikeda et al.
patent: 52-117063 (1977-10-01), None
patent: 59-121868 (1984-07-01), None
patent: 63-114172 (1988-05-01), None
patent: 2-224225 (1990-09-01), None
patent: 2-299261 (1990-12-01), None
patent: 3-61332 (1991-06-01), None
patent: 4-218956 (1992-08-01), None
patent: 4-277624 (1992-10-01), None
patent: 7-263577 (1995-10-01), None
patent: 7-321234 (1995-12-01), None
D. Chen et al., “A New Device Interconnect Level Using Sub-Micron VLSI”, Hewlett Package Laboratories, IEDM 84, pp. 118-121.
T. Tang et al., “VLSI Local Interconnect Level Using Titanium Nitride”, Semiconductor Process and Design Center, IEDM 1985, pp. 590-593.
Fukami Akira
Iida Masaya
Ikeda Shuji
Kikushima Ken'ichi
Mitani Shinichiro
Antonelli, Terry Stout & Kraus, LLP.
Lee Calvin
Renesas Technology Corp.
LandOfFree
Semiconductor integrated circuit device and process for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and process for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and process for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4046879