Semiconductor integrated circuit device and process for...

Semiconductor device manufacturing: process – Forming schottky junction – Using refractory group metal

Reexamination Certificate

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C438S630000, C438S651000, C438S683000, C438S755000

Reexamination Certificate

active

11396000

ABSTRACT:
Formation of an WNXfilm24constituting a barrier layer of a gate electrode7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNXfilm24is suppressed in the heat treatment step after the formation of the gate electrode7A.

REFERENCES:
patent: 4282270 (1981-08-01), Nozaki et al.
patent: 4505028 (1985-03-01), Kobayashi et al.
patent: 5088314 (1992-02-01), Takashi
patent: 5202096 (1993-04-01), Jain
patent: 5387540 (1995-02-01), Poon et al.
patent: 5693578 (1997-12-01), Nakanishi et al.
patent: 5719410 (1998-02-01), Suehiro et al.
patent: 6066508 (2000-05-01), Tanabe et al.
patent: 6856001 (2005-02-01), Rhodes
patent: 2001/0042344 (2001-11-01), Ohmi et al.
patent: 2001/0050686 (2001-12-01), Allen
patent: 2002/0011632 (2002-01-01), Komori
patent: 2002/0056874 (2002-05-01), Ohtake et al.
patent: 0 964 437 (1999-12-01), None
patent: 56-107552 (1981-08-01), None
patent: 59-10271 (1984-01-01), None
patent: 60-72229 (1985-04-01), None
patent: 60-89943 (1985-05-01), None
patent: 60-107840 (1985-06-01), None
patent: 60-123060 (1985-07-01), None
patent: 61-127123 (1986-06-01), None
patent: 61-127124 (1986-06-01), None
patent: 61-150236 (1986-07-01), None
patent: 61-152076 (1986-07-01), None
patent: 61-267365 (1986-11-01), None
patent: 1-94657 (1989-04-01), None
patent: 2-35775 (1990-02-01), None
patent: 3-119763 (1991-05-01), None
patent: 3-147328 (1991-06-01), None
patent: 5-141871 (1993-06-01), None
patent: 5-144804 (1993-06-01), None
patent: 5-152282 (1993-06-01), None
patent: 6-115903 (1994-04-01), None
patent: 6-120206 (1994-04-01), None
patent: 6-163871 (1994-06-01), None
patent: 6-333918 (1994-12-01), None
patent: 7-94716 (1995-04-01), None
patent: 7-94731 (1995-04-01), None
patent: 7-321102 (1995-12-01), None
patent: 8-83772 (1996-03-01), None
patent: 8-264531 (1996-10-01), None
patent: 9-75651 (1997-03-01), None
patent: 9-172011 (1997-06-01), None
patent: 9-298170 (1997-11-01), None
patent: 10-223900 (1998-08-01), None
patent: 10-335652 (1998-12-01), None
patent: 10-340909 (1998-12-01), None
patent: 11-26395 (1999-01-01), None
patent: 11-31666 (1999-02-01), None
patent: 11-102877 (1999-04-01), None
patent: 11-204456 (1999-07-01), None
patent: 11-330468 (1999-11-01), None
patent: 2000-22154 (2000-01-01), None
patent: 2000-36593 (2000-02-01), None
patent: 2000-68502 (2000-03-01), None
patent: 2000-118491 (2000-04-01), None
patent: 2000-294562 (2000-10-01), None
patent: 2000-331978 (2000-11-01), None
patent: 2000-349285 (2000-12-01), None
patent: 2001-7329 (2001-01-01), None
patent: 2001-15754 (2001-01-01), None
patent: 2001-189448 (2001-07-01), None
patent: 2002-16248 (2002-01-01), None
patent: WO97/28085 (1997-08-01), None
patent: WO98/39802 (1998-09-01), None
Maeda, K.,Latest LSI Processing Technology, Kogyo Chosakai Publishing Co., 1983, pp. 111-113 (with English translation).
Yamada, M.,Handbook of Semiconductor Processing, Ch. 1, Section 17, pp. 153-157, Oct. 15, 1996.
A. Noya et al., “Barrier Properties of W2N and ZrN films in poly-metal gate electrodes”,Technical Report of The Institute of Electronics, Information and Communication Engineers, Oct. 1999, pp. 57-62 (with English Abstract).
Yasushi Akasaka et al., “Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing,”IEEE Transactions on Electron Devices, vol. 43, No. 11, Nov. 1996, pp. 1864-1869.
K. Nakajima et al., “Formation Mechanism of Ultrathin WSiN Barrier Layer in a W/WNx/Si System,”Applied Surface Science 117/118(1997), pp. 312-316.
Gekkan,Semiconductor World, vol. 14, No. 14, Nov. 1995, pp. 161-165.
F. Ohtake et al., “A Thin Amorphous Silicon Buffer Process for Suppression of W polymetal Gate Depletion in PMOS”,2000 Symposium on VLSI Technology Digest of Technical Papers, Jun. 13-15, 2000, pp. 74-75.
E. Kolawa et al., “WxN1-xAlloys as Diffusion Barriers between Al and Si”, J. Appl. Phys. 64 (5), Sep. 1, 1988, pp. 2787-2789.
J. Jung et al., “A Fully Working 0.14 μm DRAM Technology with Polymetal (W/WNx/Poly-Si) Gate”,Electron Devices Meeting, IEDM Technical Digest, Dec. 10-13, 2000, pp. 365-368.
K. Nakajima et al., “Poly-metal Gate Process-Ultrathin WSiN Barrier Layer Impermeable to Oxidant In-diffusion During Si Selective Oxidation,” Advanced Metallization Conference Japan Session, Tokyo University, 1995.
Y. Hiura et al., “Integration Technorology of Polymetal (W/WSiN/Poly-Si) Dual Gate CMOS for 1Gbit DRAMs and Beyond”,Electron Devices Meeting, IEDM Technical Digest, Dec. 1998, pp. 389-392.
K. Nakamura et al., “Hydrogen-Radical-Balance Steam Oxidation Technology for Ultra-Thin Oxide with High Reliability,”Proceedings of the 45thSymposium on Seminconductors and Integrated Circuits Technology, Tokyo, Japan, Dec. 1993, pp. 128-133.
E. Kneer et al., “Electrochemistry of Chemical Vapor Deposited Tungsten Films with Relevance to Chemical Mechanical Polishing,”J. Electrochem. Soc., vol. 143, No. 12, Dec. 1996, pp. 4095-4100.

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