Semiconductor integrated circuit device and process for...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21545

Reexamination Certificate

active

07154164

ABSTRACT:
A large area dummy pattern DL is formed in a layer underneath a target T2region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

REFERENCES:
patent: 5292689 (1994-03-01), Cronin et al.
patent: 5308682 (1994-05-01), Morikawa
patent: 5321304 (1994-06-01), Rostoker
patent: 5441915 (1995-08-01), Lee
patent: 5459093 (1995-10-01), Kuroda
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5614445 (1997-03-01), Hirabayashi
patent: 5621241 (1997-04-01), Jain
patent: 5885856 (1999-03-01), Gilbert
patent: 5892277 (1999-04-01), Ikemizu et al.
patent: 5903489 (1999-05-01), Hayano
patent: 5929528 (1999-07-01), Kinugawa
patent: 6020616 (2000-02-01), Bothra et al.
patent: 6077784 (2000-06-01), Wu
patent: 6087733 (2000-07-01), Maxim
patent: 6130139 (2000-10-01), Ukeda et al.
patent: 6171976 (2001-01-01), Cheng
patent: 6255697 (2001-07-01), Yoo et al.
patent: 6261883 (2001-07-01), Koubuchi et al.
patent: 6285066 (2001-09-01), Meyer
patent: 6326278 (2001-12-01), Kumoro
patent: 6346736 (2002-02-01), Ukeda et al.
patent: 6433438 (2002-08-01), Koubuchi et al.
patent: 6664642 (2003-12-01), Koubuchi et al.
patent: 6693315 (2004-02-01), Kuroda et al.
patent: 2004/0032009 (2004-02-01), Fang et al.
patent: 2005/0127471 (2005-06-01), Sawamura
patent: 2005/0248000 (2005-11-01), Chen et al.
patent: 5275527 (1993-10-01), None
patent: 7-74175 (1995-03-01), None
patent: 07-092838 (1995-04-01), None
patent: 8314762 (1996-11-01), None
patent: 923844 (1997-06-01), None
patent: 9181159 (1997-07-01), None
patent: 10-335333 (1998-12-01), None
patent: 410335333 (1998-12-01), None
patent: 11-233411 (1999-08-01), None
patent: 9615552 (1996-05-01), None
Lee, et al., “An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI)”, 1996, Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Semiconductor integrated circuit device and process for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit device and process for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and process for... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3668913

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.