Semiconductor integrated circuit device, and process and apparat

Details Semiconductor integrated circuit device, and process and apparat Semiconductor integrated circuit device, and process and apparat

1997-02-18

1999-06-08

Graybill, David

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438 16, 438 17, 438109, 438111, 438112, 438124, 26427217, H01L 2152, H01L 2156, H01L 2158, H01L 2160

Patent

active

059100109

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing it and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device having a small-size/high-performance multi-chip module.


BACKGROUND ART

A memory module, as represented by the SIMM (i.e., Single In-line Memory Module), is widely utilized as a semiconductor memory to be mounted on an engineering workstation (EWS) or a computer. The SIMM is usually given a construction in which a semiconductor chip having a memory LSI such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory) is packaged into an LSI package such as an SOJ (Small Out-line J-leaded Package) and in which a plurality of semiconductor chips are mounted on one or both sides of a printed circuit board.
For the EWS or a parallel processing computer of recent years, however, there is required a memory (RAM) of large capacity for processing massive data at a high speed. In order to meet this requirement, therefore, a three-dimensional technique has been investigated for the memory module. This is because a system having an LSI package planarly (or two-dimensionally) over a printed circuit board has a larger size in the printed circuit board as the memory capacity grows larger.
As a specific example of a three-dimensional memory module, there is known the structure (as disclosed on pp. 33 to 39 of "Electronic Materials" issued on Sep. 1, 1993 by Kogyo Chosakai) in which several layers of very thin LSI packages such as TSOP (Thin Small Out-line Package) are stacked, with the printed circuit boards on their two side walls and in which the leads of the TSOP are held by the side boards.
According to the three-dimensional memory module of this kind, more LSI packages can be mounted on the printed circuit board of the same area to realize a small-size/large-capacity memory module. Moreover, the wiring length for connecting the packages can be made smaller than that of the case that the LSI packages are planarly mounted on the printed circuit board, to raise a great advantage in the aspect of high speed.
However, the three-dimensional memory module of the conventional structure, in which the very thin LSI packages such as TSOP are stacked, has found it difficult to reduce the size of the module and the heat resistance of the package at the same time.
Specifically, when the LSI packages such as TSOP are stacked, the thickness of the resin between the upper and lower semiconductor chips is doubled to increase the heat resistance of the package. In order to lower this heat resistance, therefore, a suitable gap has to be established between the packages so that the external size of the module in the vertical direction is enlarged.
Effective means for reducing the size of the three-dimensional memory module is to package a plurality of semiconductor chips into one package. With this means, the thickness of the resin between the upper and lower semiconductor chips is thinned to reduce not only the external size of the package in the vertical direction but also the heat resistance of the package.
Merely by packaging a plurality of semiconductor chips simply into one package, however, it is impossible to provide a highly reliable memory module. Specifically, when a plurality of semiconductor chips are packaged into one package, it is anticipated that the temperature difference between the center portion and the peripheral portion of the package may become large to cause a serious heat stress in the package. Hence, it is essential to provide a structure design for dissipating the heat of the central portion of the package quickly to the outside.
When a plurality of semiconductor chips are packaged into one package, their testing, screening and aging methods are serious problems. Specifically for the module in which a plurality of semiconductor modules are packaged into one package, none of the semiconductor chips can be replaced even if it is found defective afte

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Electronic Materials, Sep. 1, 1993, Kogyo Chosakai, pp. 33-39.

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