Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1994-05-03
1995-11-28
Meier, Stephen D.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257777, H01L 2348, H01L 2962
Patent
active
054710952
ABSTRACT:
There is disclosed a semiconductor integrated circuit device including an element-to-element line (10A) of a quadrangular (rectangular) configuration in cross section having horizontal upper and lower surfaces, with its lower surface corners on the side of a semiconductor substrate (1) chamfered on the slant. This increases the horizontal distance between adjacent lines and decreases the height of the line, permitting the adjacent line-to-line parasitic capacitance to be lower than that of the prior art line of a quadrangular configuration in cross section under the same height and line-to-line horizontal distance conditions. The line-to-substrate parasitic capacitance is also permitted to be lower for similar reasons. The semiconductor integrated circuit device is thus provided in which the parasitic capacitances generated by forming lines are minimized.
REFERENCES:
patent: 5018005 (1991-05-01), Lin et al.
patent: 5083186 (1992-01-01), Okada et al.
T. Sakurai and K. Tamaru, "Simple Formulas for Two- and Three-Dimensional Capacitances", IEEE Transactions on Electron Devices, v. ED-30, No. 2, Feb. 1983, pp. 183-185.
Arakawa Takahiko
Kaminaga Isamu
Katoh Shuuichi
Matsue Shuuichi
Ueda Masahiro
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
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