Semiconductor integrated circuit device and method of arranging

Details Semiconductor integrated circuit device and method of arranging Semiconductor integrated circuit device and method of arranging

1993-07-22

2000-09-19

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257210, H01L 2710

Patent

active

061216445

ABSTRACT:
Input/output terminals 10 made of a first aluminium wiring layer are provided within cells 3a to 3c in the same cell row 30. A plurality of mains 7a to 7c made of a second aluminium wiring layer, which are electrically independent of the input/output terminals 10 of the standard cells 3a to 3c, a power source wire 1 and a grounding wire 2, are arranged between the input/output terminals 10 of the standard cells 3 to be connected so that they extend in parallel with a cell row extending direction. Via holes 8 are provided in regions in which the input/output terminals 10 overlap the mains 7 two-dimensionally to make electrical connection between the input/output terminals 10 and the mains 7. Since the wirings in the same cell row are executed within the cells in the cell row, an integration degree can be improved.

REFERENCES:
patent: 4249193 (1981-02-01), Balyoz et al.
patent: 4623911 (1986-11-01), Pryor
patent: 4651190 (1987-03-01), Suzuki et al.
patent: 4716450 (1987-12-01), Hashishita
"New Design Approach for Configurable Data-Path", Proceedings of the IEEE CICC, pp. 14.5.1-14.5.4, 1990.

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