Active solid-state devices (e.g. – transistors – solid-state diode – Avalanche diode – With means to limit area of breakdown
Reexamination Certificate
2001-01-25
2004-10-12
Baumeister, B. William (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Avalanche diode
With means to limit area of breakdown
C257S551000, C257S605000
Reexamination Certificate
active
06803644
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. In particular, the present invention relates to a technique that is effective to apply a clamp element of an internal boosting circuit to a semiconductor integrated circuit device comprising a zener diode.
BACKGROUND OF THE INVENTION
An EEPROM (Electrically Erasable and Programmable ROM) that is a type of memory LSI comprises a constant voltage generating circuit for applying a voltage (Vpp) higher than a power supply voltage (Vcc) to a gate electrode when rewriting (writing and erasing) data. A zener diode as a clamp element for voltage stabilization is connected to the boosting circuit in the constant voltage generating circuit, whereby the rewrite voltage (Vpp) is constantly supplied to the EEPROM. A publicly known zener diode of such type is disclosed in Japanese Patent Laid-open No. 64-59949, dated Mar. 7, 1989, for example.
The zener diode described in the above-mentioned Laid-open No. 64-59949 is composed of: an n
+
type semiconductor region formed in a p type well of a semiconductor substrate; and a p
+
type semiconductor region formed in a p type well at a lower part of this n
+
type semiconductor region. An area surrounding a planar pattern on the p
+
type semiconductor region is smaller than that of the n
+
type semiconductor region, and the p
+
type semiconductor region is located so as to be substantially centered to that of the n
+
type semiconductor region. In this manner, the p
+
type semiconductor region and n
+
type semiconductor region have such a structure as is closed in the semiconductor substrate, so that the structure can prevent an occurrence of a problem with a leakage current due to an interface level of an interface between the semiconductor substrate and an insulation film (silicon oxide film) on an upper part thereof.
To the p
+
type well in which the above p
+
type semiconductor region is formed and the n
+
type semiconductor region is formed thereon, a wire is connected through a connection hole provided in an insulation film that covers upper parts of both. To the n
+
type semiconductor region, a wire is connected through the center thereof, i.e., a connection hole formed at the insulation film located in the upper part of the p
+
type semiconductor region.
SUMMARY OF THE INVENTION
As an EEPROM becomes fine and highly integrated, a junction depth between source and drain of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) that constitutes a memory cell or a peripheral circuit is gradually made more shallow, and accordingly, a junction depth between the n
+
type semiconductor region and p
+
type semiconductor region that constitutes a zener diode in the constant voltage generating circuit is gradually made more shallow as well. In addition, since the connection hole for connecting the n
+
type semiconductor region or p
+
type semiconductor region to a wire becomes small in diameter, it is difficult to form the connection hole by dry etching.
Therefore, in the zener diode as described in the above-mentioned Laid-open No. 64-59949, when a connection hole is formed for connecting the n
+
type semiconductor region and a wire to each other, a difference in diameter between an element and a connection hole formed in a highly dense memory region or the like causes a substrate around the greater connecting hole in diameter in a zener diode forming region to be excessively shaved off. And, since thickness (the junction depth) of the n
+
type semiconductor region of a pn junction at a bottom of the connection hole (p
+
type semiconductor region
+
type semiconductor region) becomes extremely thin, an increase of a leakage current caused by a tunnel current or the like becomes obvious.
As a result, there occurs a problem that the leakage current at a fall (breakdown) start voltage of a zener diode exceeds 10 &mgr;A, for example, and that a desired rewrite voltage cannot be obtained because a clamp voltage is lowered.
An object of the present invention is to provide a technique capable of reducing a leakage current of a zener diode.
Another object of the present invention is to provide a technique capable of suppressing a substrate shaving caused when a connection hole is formed for connecting a substrate and a wire to each other.
The foregoing and the other objects and new characteristics of the present invention will be apparent from a description of the present specification and the accompanying drawings thereof.
Example featured aspects of the present invention, disclosed in the present application, will be briefly described by the following:
(1) A semiconductor integrated circuit device of the present invention includes a semiconductor substrate of a first conductivity type; a zener diode comprised of a first semiconductor region of a second conductivity type formed in a primary face (i.e., principal surface) of the semiconductor substrate, and a second semiconductor region of the first conductivity type formed in the semiconductor substrate at a bottom portion of said first semiconductor region and being smaller in area, defined by a planar pattern thereof, than said first semiconductor region, wherein a plurality of first connection holes for electrically connecting said first semiconductor region and a wire to each other are arranged in a region located outside a junction formed between said first semiconductor region and said second semiconductor region.
(2) A semiconductor integrated circuit device of the present invention includes a semiconductor substrate of a first conductivity type; a zener diode comprised of a first semiconductor region of a second conductivity type formed in a primary face (i.e., principal surface) of the semiconductor substrate, and a second semiconductor region of a first conductivity type formed in the semiconductor substrate at a bottom portion of said first semiconductor region and being smaller in area, defined by a planar pattern thereof, than said first semiconductor region, wherein a plurality of first connection holes for connecting said first semiconductor region and a wire to each other are arranged in a region located outside a junction formed between said first semiconductor region and said second semiconductor region, and wherein each of said plurality of first connection holes is spaced from each other so that a pitch between the adjacent first connection holes is greater than a maximum pitch between connection holes of the circuit.
(3) A semiconductor integrated circuit device of the present invention according to the above-mentioned (1) or (2), wherein each of said plurality of first connection holes is spaced from each other so that a pitch between the adjacent first connection holes is greater than a minimum pitch between connection holes of the circuit.
(4) A method of manufacturing a semiconductor integrated circuit device of the present invention comprises:
(a) forming a semiconductor region of a first conductivity type in a first region on a primary face (i.e., principal surface) of a semiconductor substrate of a first conductivity type, and then forming, on said semiconductor substrate located in a top portion of the semiconductor region of said first conductivity type, a semiconductor region of a second conductivity type that has a greater area of a planar pattern than the semiconductor region of said first conductivity type, and thereby forming a zener diode comprised of the semiconductor region of said first-conductivity type and the semiconductor region of said second conductivity type;
(b) forming an insulation film on the primary face of said semiconductor substrate, and then forming a plurality of connection holes in said insulation film at an upper part of a region located outside a junction formed between the semiconductor regions of said first and second conductivity types; and
(c) forming a wire a
Kamigaki Yoshiaki
Minami Shin-ichi
Owada Fukuo
Yasuoka Hideki
Antonelli Terry Stout & Kraus LLP
Baumeister B. William
Renesas Technology Corp.
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