Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2002-02-15
2003-11-04
Tran, M. (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S185240
Reexamination Certificate
active
06643210
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and the method of controlling the same.
An EEPROM (electrically erasable programmable read-only memory), one of different kinds of nonvolatile memories, has a plurality of memory cells. A known memory Ad cell consists of a floating gate field effect transistor (FET) with a double-layer electrode structure composed of a source region, a drain region, a channel region, a floating gate electrode provided on the channel region via an insulating film, and a control gate electrode provided on the floating gate electrode via an insulating film. A control signal is sent to the control gate electrode via a word line. As a structure of the word line, a structure constituted by a main word line and a sub word line connected to the main word line via a switching element is known. Such a structure is employed in a conventional flash memory, in which a large amount of currents flow into memory cells during a read or write operation. This is because, when a structure composed of a bit line and a sub bit line is employed in the flash memory, a voltage across the switching element for connecting the main bit line and the sub bit line falls markedly and this may result in misreading of the memory cells or an increased load on a circuit for generating a write voltage.
The flash memory has a plurality of memory blocks with memory cells arranged in a matrix therein. Each of the memory blocks is provided with a bit line decoder and bit lines, independently of the other memory blocks. Information is read from the flash memory having such a configuration as follows.
First, a switching element connecting a main word line and a sub word line is turned on to select the main word line and the sub word line, and then a voltage required for a read operation is applied to the sub word line through the main word line. Subsequently, a predetermined voltage is applied to a selected bit line to select a memory cell. Then, a current flowing through the selected memory cell is compared with a predetermined reference value by a differential amplifier, and a result determined based on the comparison is output as data.
At this time, when a charge remains in drains of unselected memory cells commonly connected to the sub word line, that is, memory cells for which the associated word line is selected and of which the sources have a low potential, the charge accumulated in the drain is pulled out, or extracted to the source side. In the flash memory, since memory cells in the same memory block usually have their sources commonly connected, currents to the sources in these unselected memory cells raise a source potential and may result in misreading.
Furthermore, since the charge in the drain is pulled to the source side in the unselected memory cells, hot electrons, that is, high-energy electrons are generated, and the electrons are injected into the floating gate electrodes of the unselected memory cells. Therefore, the threshold value of the unselected memory cells may rise.
Therefore, in general, the bit lines connected to the drains of the memory cells are connected to a discharge circuit via a switching element so that the charge in the drains of the memory cells is extracted via the bit lines when the flash memory is in a standby state, that is, a non-access state.
Meanwhile, in the conventional flash memory, when electrons are extracted from a floating gate electrode of a memory cell (an erase operation is assumed here), a method of applying a negative voltage to a word line is employed in general. In this case, the following problems occur in a flash memory having main word lines and sub word lines, the latter being provided in each memory block independently of the other memory blocks.
The switching element connecting the main word line and the sub word line needs to transmit a positive voltage during read and write operations and a negative voltage during an erase operation. Therefore, voltage control of the switching element becomes complicated and a control circuit provided to apply the positive voltage and the negative voltage to the switching element disadvantageously enlarges the memory.
An example of a semiconductor integrated circuit device having main word lines and sub word lines like the above-described flash memory is shown in FIG.
5
. The semiconductor integrated circuit device has a memory cell region M made up of a plurality of memory blocks MB
0
, . . . , MB
X
and main word lines WLM
0
, . . . , WLM
n
commonly connected to the plurality of memory block MB
0
, . . . , MB
X
. Each memory block MB
0
, . . . , MB
X
has a plurality of memory cells MC
00
, . . . , MC
nm
arranged in a matrix. Each memory cell MC
00
, . . . , MC
nm
, consists of a floating gate type field effect transistor having a control electrode and a floating electrode. Furthermore, in each of the memory blocks MB
0
, . . . , MB
X
, drain regions of the memory cells in the same column are commonly connected by an associated bit line BL
0
, . . . , or BL
m
, while control gate electrodes of the memory cells in the same row are commonly connected by a sub word line WLS
0
, . . . , or WLS
n
. Furthermore, P-type MOS (Metal Oxide Semiconductor) field effect transistors LWS
00
, . . . , LWS
Xn
for selecting sub word lines WLS
0
, . . . , WLS
n
are provided in each of the memory blocks MB
0
, . . . , MB
X
. The P-type MOS field effect transistors LWS
00
, . . . , LWS
Xn
of each memory block are connected to a sub word line selecting circuit
100
via an associated memory block selecting gate line BS
0
, . . . , or BS
X
and to a voltage switching circuit
200
for switching between a back bias high voltage and a voltage VSS via an associated back bias supply line NW
0
, . . . , or NW
X
. Furthermore, to pull out a charge accumulated in the bit line BL
0
, . . . , BL
m
, the bit line BL
0
, . . . , BL
m
is grounded via a MOS field effect transistor DC
0
, . . . , DC
m
. The MOS field effect transistor DC
0
, . . . , DC
m
is controlled by a discharge selecting gate line DDC
0
, . . . , DDC
m
. Furthermore, the main word line WLM
0
, . . . , WLM
n
and the sub word line WLS
0
, . . . , WLS
n
are connected via the P-type MOS field effect transistor LWS
00
, . . . , LWS
Xn
. A voltage is supplied from a main word line decoder MWD to the main word line WLM
0
, . . . , WLM
n
. Furthermore, in the sub word line selecting circuit
100
from which a voltage is supplied to a P-type MOS field effect transistor LWS
00
, . . . , LWS
Xn
, control for generating a negative voltage required depending on the operation is performed. As is obvious, since the field effect transistors DC
0
, . . . , DC
m
, the sub word line selecting circuit
100
and the voltage switching circuit
200
are required in each memory block MB
0
, . . . , MB
X
, the circuit size becomes large.
Hereafter, voltage control during a read operation in the semiconductor integrated circuit device will be explained below with reference to FIG.
6
. In
FIG. 6
, it is assumed that a memory cell MC
00
in the memory block MB
0
is selected.
In a read operation, as shown in
FIG. 6
, a voltage of about 5 V is applied to the control gate electrode of the memory cell MC
00
, while a voltage of about 1 V is applied to the drain region of the memory cell MC
00
. At this time, a voltage to be applied to the control gate electrodes of unselected memory cells MC
10
, . . . , MC
1m
; . . . ; MC
n0
, . . . , MC
nm
in the memory block MB
0
needs to be set at 0 V. Therefore, a voltage of −5 V is applied to the memory block selecting gate line BS
0
, and the main word lines WLM
1
−WLM
n
at 0 V are electrically connected to the associated sub word line WLS
1
−WLS
n
.
Voltage control during a write operation in the semiconductor integrated circuit device is explained below with reference to FIG.
7
. In
FIG. 7
, it is assumed that a memory cell MC
00
in the memory block MB
0
is selected.
During a write operation, as shown in
FIG. 7
, a voltage of about 10 V is appli
Sharp Kabushiki Kaisha
Tran M.
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