Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-07-10
2003-05-13
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C257S296000, C257S510000
Reexamination Certificate
active
06562695
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device and to a technique for manufacturing the same; and, more particularly, the invention relates to a device isolation structure for forming fine or micro MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and a technique effective for application to a forming process thereof.
TECHNICAL BACKGROUND
With scale-down and high integration of semiconductor chips or elements, the introduction of a shallow groove isolation (SGI), of a type in which an insulating film is embedded inside each groove defined in a silicon substrate, is proceeding to provide a device isolation structure that serves as an alternative to a local oxidization of silicon (LOCOS) method.
The above-described shallow groove isolation is considered to be advantageous from the point of view of ensuring sub-threshold characteristics and reduction in junction leakage and a backgate effect, as compared with the LOCOS method, because (a) the device isolation interval or space can be reduced, (b) it is easy to control the film thickness for device isolation and set a field reverse voltage, and (c) an inversion preventive layer can be separated from a diffused layer and a channel region by separately implanting an impurity in side walls of the inside of each groove and the bottom thereof.
A common method for forming the shallow groove isolation is as follows: First of all, a silicon substrate is subjected to thermal oxidation and a thin silicon oxide film is formed on the surface thereof. Thereafter, a silicon nitride film is deposited thereabove by a CVD (Chemical Vapor Deposition) method. Next, each silicon nitride film lying in a device isolation region is removed by dry etching using a photoresist film as a mask. Thereafter, trenches or grooves are defined in the substrate by dry etching with the silicon nitride films being left in each active region as masks.
Next, a thick silicon oxide film is deposited on the substrate, including the interiors of the grooves, by the CVD method. Thereafter, the substrate is subjected to a thermal process, and the silicon oxide films embedded inside the grooves are elaborately densified. Thereafter, the silicon oxide films above the silicon nitride films are removed by a polishing process, such as etchback or chemical mechanical polishing (CMP) or the like, and the unnecessary silicon nitride films are then removed, whereby shallow groove isolations are completed. Shallow groove isolations are discussed, for example, in Japanese Laid-Open Patent Application No. Hei 02-260660, No. Hei 04-303942, No. Hei 08-97277 etc.
SUMMARY OF THE INVENTION
The present inventors have found that thinning (local thinning) occurs in that a gate oxide film formed on the surface of the substrate corresponding to each active region would locally be thinned at a peripheral portion of the active region, and a phenomenon (called a MOS-IV kink characteristic) in which a drain current tends to flow in response to a low gate voltage, have developed in the above-described device isolation structure. As a measure for solving these problems, the present inventors have considered a technique for rounding the peripheral portion of the active region (effecting round processing on it).
As a result of examining this approach, the present inventors have found that the (round processing) technique for rounding the peripheral portion of each active region, after the grooves are defined in the substrate, has a problem in that, since it requires a high-temperature thermal oxidizing process, a thermal oxide film formed on an inner wall of each groove due to the thermal oxidizing process at the time of round processing tends to grow to the active region side, thereby reducing the size of the active region, and, hence, this provides a hindrance to high integration and scale down of each MISFET.
Namely, a problem arises in that, when the round processing (round) is insufficient, thinning (local thinning) occurs in which a gate oxide film is thinly formed at a peripheral portion of each pointed active region upon oxidation for forming the gate oxide film, and a variation in the threshold voltage of each MISFET is produced due to a MOS-IV kink characteristic. It is necessary to sufficiently effect round processing (round) as an effective measure. However, when sufficient round is applied to the peripheral portion of the active region, the active region (particularly, in the direction of a gate width of each MISFET) becomes narrow. Therefore, the size (particularly, the gate width of the MISFET) of the active region cannot be ensured, and the semiconductor elements cannot be scaled down. In addition, this provides a hindrance to the desire for the width of each shallow groove isolation to be miniaturized and the semiconductor elements to be scaled down, so as to be brought into high integration.
An object of the present invention is to provide a technique that is capable of providing an advancement in the scale-down of MISFETS.
Another object of the present invention is to provide a technique that is capable of promoting the scale-down of the width of each shallow groove isolation.
The above and other objects and novel features of the present invention will become apparent from the description provided in the present specification from and the accompanying drawings.
Summaries of typical aspects and features of the invention disclosed in the present application will be described briefly as follows:
(1) A semiconductor integrated circuit device according to the present invention comprises a plurality of active regions each having an island-shaped plane pattern whose periphery is surrounded by shallow groove isolations, which are disposed on a main surface of a substrate so as to have predetermined intervals in a first direction, and semiconductor elements formed in the plurality of active regions, and wherein the sum of the width of each active region extending in the first direction and the space defined between the adjacent active regions constitutes a minimum pitch in the first direction, and the width of each active region in the first direction is set larger than one-half the minimum pitch.
(2) In a semiconductor integrated circuit device according to the item 1, the half of the minimum pitch is a minimum processing size determined according to a resolution limit of photolithography.
(3) In a semiconductor integrated circuit device according to the item 1 or 2, the semiconductor elements are respectively coupled to interconnections disposed so as to have predetermined intervals, and the width of each interconnection and the space between the adjacent interconnections are respectively set to the minimum pitch.
(4) A semiconductor integrated circuit device according to the present invention comprises a plurality of active regions each having an island-shaped plane pattern whose periphery is surrounded by shallow groove isolations, which are disposed on a main surface of a substrate so as to have predetermined intervals in a first direction, and semiconductor elements formed in the plurality of active regions, and wherein the sum of the width of each active region extending in the first direction and the space defined between the adjacent active regions is set to twice a minimum processing size determined according to a resolution limit of photolithography, the width of each active region is greater than or equal to the minimum processing size and the space defined between the adjacent active regions is less than or equal to the minimum processing size.
(5) In a semiconductor integrated circuit device according to the item 2, 3 or 4, the semiconductor elements are respectively coupled to interconnections disposed so as to have predetermined intervals, and the width of each interconnection and the space between the adjacent interconnections are respectively set to the minimum processing size determined according to the resolution limit of photolithography.
(6) In a semiconductor integrated circuit device according to the item 3 or 5
Horibe Shinichi
Ichizoe Hiroyuki
Ikeda Shuji
Ishitsuka Norio
Kojima Masayuki
Antonelli,Terry, Stout & Kraus, LLP
Elms Richard
Hitachi , Ltd.
Owens Beth E.
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