Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
1998-12-08
2001-04-17
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C327S512000
Reexamination Certificate
active
06218889
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor integrated circuit device and semiconductor integrated circuit device technology and, more particularly, to an art which can be usefully applied to a so-called semiconductor integrated circuit device to be employed in a circuit which uses a large amount of power, whose device has a power MIS (Metal Insulator Semiconductor) transistor having a gate insulating film or a power MOS (Metal Oxide Semiconductor) transistor having a gate oxide film, as well as to a method of manufacturing such semiconductor integrated circuit device.
BACKGROUND OF THE INVENTION
Power MIS transistors have high breakdown voltage (withstand voltage), high thermal stability and high gain, and can be easily used to realize a construction for power amplification. For this reason, the power MIS transistors are widely used as power devices for switching power sources, motor control power devices, power devices for vehicles or the like, and, in recent years, have been becoming finer and finer to realize far higher performance.
In many cases, to ensure a certain degree of electrostatic breakdown strength, a protection diode (a zener diode) is provided in a semiconductor chip in which a power MIS transistor is formed, and the protection diode is electrically connected between the gate and the source of the power MIS transistor.
In some types of power MIS transistors having built-in protection functions, not only a protection diode but also another protection circuit such as a thermal sense circuit is provided in a semiconductor chip in which a power MIS transistor is formed, and such protection circuit is electrically connected to between the gate and the source of the power MIS transistor.
In general, such power MIS transistor uses a package having a three-terminal structure. In this case, a gate electrode and a source electrode are disposed on a principal surface of the semiconductor chip in which the power MIS transistor is formed, and a drain terminal is disposed on the reverse surface of the semiconductor chip.
SUMMARY OF THE INVENTION
However, the present inventors have found out that the above-described semiconductor integrated circuit device technology of providing a power MIS transistor and other elements or circuits in a single semiconductor chip has the following problems.
One problem is that since a protection circuit or the like is connected to the power MIS transistor, a voltage which is necessary for screening of the power MIS transistor itself cannot be applied in a screening step, so that a satisfactory screening effect cannot be realized.
In a device such as a power MIS transistor whose gate insulating film has a large area, since defects in the gate insulating film often cause a breakdown of an element or a defective characteristic, it is important to ensure the reliability of the gate insulating film. Normally, a gate insulating film (silicon oxide film) of approximately 500Å thick has an intrinsic withstand voltage of approximately 40 V, and needs a screening voltage of approximately 30 V. However, in a power MIS transistor in which a protection diode (a zener diode) or the like is electrically connected between the gate and the source (or the gate and the drain) of the power MIS transistor, a screening voltage is set to a value as close as possible to the guaranteed withstand voltage of the power MIS transistor in terms of the zener voltage of the protection diode in order to ensure a satisfactory level of electrostatic breakdown strength. As a result, it is merely possible to apply a voltage of approximately as low as 22 V which is far lower than a desired voltage (for example, approximately 30 V). In addition, in the power MIS transistor which includes the protection circuit, a gate voltage is clamped by a zener diode and, at the same time, the screening voltage is limited by the withstand voltage of a lateral MIS transistor which constitutes another circuit (the protection circuit), so that a screening voltage of approximately as low as 24 V can only be applied. Incidentally, the thickness of a gate insulating film (a gate oxide film) of the lateral MIS transistor which constitutes the aforesaid other circuit (the protection circuit) is generally smaller than that of a gate insulating film (a gate oxide film) of the power MIS (MOS) transistor. Accordingly, the lateral MIS transistor is lower in withstand voltage than the power MIS (MOS) transistor.
One available method for avoiding such a problem is to increase the time of application of the screening voltage. However, if satisfactory screening is to be performed with a low voltage, the time of application of the screening voltage needs to be increased, so that the problem of a longer inspection time occurs.
Arts which take into account the above-described problems of the power MIS transistor are disclosed in, for example, Japanese Patent Laid-Open Nos. 67661/1993, 142711/1995 and 283370/1995.
The above-identified Japanese Patent Laid-Open No. 67661/1993 discloses a structure in which two constant-voltage diodes having different withstand voltages are provided between the gate and the source of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this structure, during screening, a switching element is turned off, and a screening voltage is applied to the gate and the source of the power MOSFET with a constant-voltage diode of lower withstand voltage being isolated from the power MOSFET, and after screening, the switching element is turned on and the constant-voltage diode of lower withstand voltage is electrically connected between the gate and the source of the power MOSFET. However, in this art, the number of terminals to be led out from a semiconductor chip is increased and compatibility with normal three-terminal packages becomes a problem, and, in addition, the number of elements increases and the circuit construction becomes complicated.
The above-identified Japanese Patent Laid-Open No. 142711/1995 discloses a structure in which a gate voltage applying circuit is provided at the front stage of the gate of a power MOSFET. In this art, a zener diode which sets a gate voltage to be used during the operation of the power MOSFET and a zener diode which adds voltages together and applies the voltage sum during an inspection of a gate voltage are connected in series, and, during the inspection of a gate voltage, a switching element is turned off to apply the voltage obtained by adding together the zener voltages of both zener diodes. However, in this art as well, the number of terminals to be led out from a semiconductor chip is increased and compatibility with normal three-terminal packages becomes a problem, and, in addition, the number of elements increases and the circuit construction becomes complicated.
The above-identified Japanese Patent Laid-Open No. 283370/1995 discloses an art which provides the gate electrode of a power MOSFET with a testing gate terminal and executes a gate check test by applying a high voltage to the test gate terminal, and which provides a level shifting circuit unit for lowering a voltage to be applied to a control circuit, in order to prevent a high voltage from being applied to the side of the control circuit. However, in this art as well, the number of terminals to be led out from a semiconductor chip is increased and compatibility with normal three-terminal packages becomes a problem, and, in addition, since the level shifting circuit unit is newly added, the number of elements increases and the circuit construction becomes complicated.
An object of the present invention is to provide an art which is capable of rapidly and effectively performing screening on a semiconductor integrated circuit device in which a power MIS transistor and other circuits are provided on a single semiconductor substrate.
Another object of the present invention is to provide an art which is capable of rapidly and effectively performing screening on a semiconductor integrated circuit device in which a po
Fujiki Atsushi
Iijima Tetsuo
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Nguyen Linh
Tran Toan
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