Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2006-08-31
2008-09-23
Graybill, David E (Department: 2822)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S197000, C438S216000, C438S257000, C438S258000, C438S261000, C438S266000, C438S275000, C438S591000
Reexamination Certificate
active
07427537
ABSTRACT:
In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.
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Ootsuka Fumio
Tokunaga Takafumi
Yoshida Makoto
Antonelli, Terry Stout & Kraus, LLP.
Graybill David E
Renesas Technology Corp.
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