Semiconductor integrated circuit device and method for...

Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks

Reexamination Certificate

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C257S529000, C257S048000, C257S758000, C257S665000, C257S642000, C257S530000, C257S209000, C257S643000, C257S759000, C438S401000, C438S462000, C438S975000

Reexamination Certificate

active

07053495

ABSTRACT:
A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignment mark, and target mark are formed out of an identical copper film in the uppermost metal layer. External-component-connecting pad electrode, testing-processing alignment mark, and stepper alignment mark are formed out of an identical aluminum alloy film on the dielectric film. In laser-machining the fuse wire, alignment using the target mark formed in the metal layer including the fuse wire reduces alignment errors caused from the machining.

REFERENCES:
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patent: 6392300 (2002-05-01), Koike
patent: 6457169 (2002-09-01), Ross
patent: 6586282 (2003-07-01), Takasu
patent: 6784516 (2004-08-01), Daubenspeck et al.
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patent: 11121623 (1999-04-01), None
patent: 2001-035924 (2001-02-01), None
patent: 2001144197 (2001-05-01), None
patent: 2002184777 (2002-06-01), None

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