Semiconductor device manufacturing: process – Forming schottky junction
Reexamination Certificate
1999-10-19
2001-10-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Forming schottky junction
C438S253000, C438S244000, C438S396000, C438S399000
Reexamination Certificate
active
06303478
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and a method for fabricating the same and, more particularly, to a semiconductor integrated circuit device having microscopic multilayer wirings and a method for fabricating such a semiconductor integrated circuit device easily and with high precision. This invention is especially effective for application to a DRAM having a logical LSI.
BACKGROUND OF THE INVENTION
In a semiconductor integrated circuit device, particularly a DRAM (dynamic random access memory), it is very important to increase integration and make multilayer wirings microscopic. According to a first conventional approach, for example, disclosed in Laid-open Japanese Patent Application No. 06-120447, the DRAM design is structured to include two plugs, having a reverse trapezoidal cross section and with the bases thereof being smaller than the top, which are directly connected electrically to connect a diffused layer of a MOS transistor and a lower electrode of a capacitor (a storage node electrode) that consists of a polycrystal silicon, in a DRAM memory array portion.
In conventional DRAMs, a storage capacitor is, typically, placed in a lower portion of a bit line or just above it, similarly to the case of the first conventional method, described above. In that case, however, one problem is that a focus margin in photolithography cannot cover a stage difference between a memory array portion and a peripheral circuit portions (an I/O control circuit portion and a decoder portion), posing limitations to microminiaturization. Further, in the case of fabricating an LSI chip containing a logic circuit, in addition to a memory array portion having a capacitor of a DRAM, etc., the above problem creates a major drawback.
Accordingly, there is proposed a structure in which a capacitor is formed above wiring layers for the purpose of eliminating the limitations on microminiaturization by reducing the stage difference described above. For example, according to a second conventional approach, for example, in Laid-open Japanese Patent Application No. 06-085187, a plug for connecting a diffused layer of a MOS transistor and a lower electrode of a capacitor are formed after wiring layers have been formed.
The first conventional art described above has the problem that because the cross section of the plugs is of reverse trapezoid shape with the sides not vertical and the top area large, the plugs occupy a large area and an area per memory cell increases. Although a polysilicon film is used as a lower electrode of a capacitor of the memory cell array portion, because smaller resistance is required for use as plugs of peripheral circuit portions and a logic circuit portion, a metallic film such as a tungsten film, etc. is usually used. Accordingly, the memory cell array portion, the peripheral circuit portions, and the logic circuit portion require that plugs made of mutually different materials be formed through processes different for each of them, increasing the number of process steps.
Thus, the conventional arts cannot solve three problems simultaneously: (1) making a memory array portion microscopic; (2) lowering the resistance of plugs of peripheral circuit portions and a logic circuit portion; and (3) lowering fabrication cost.
On the other hand, as with the second conventional art, in the case of forming a plug for connecting a diffused layer of a MOS transistor and a lower electrode of a capacitor after forming a wiring layer, although there are required the process to form holes with a large aspect ratio and the process to form plugs by padding the holes with a metallic film, the processes are technically difficult, making it difficult to obtain satisfactory results. Especially when the depth of a connection hole exceeds 1.0 &mgr;m, the formation of the hole and the padding of a metallic film becomes very difficult, a yield decreases, and fabrication cost increases. This method requires a large alignment margin for layer alignment among multiple layers in photolithography performed to form connection holes, so that a unit memory cell area increases.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a semiconductor integrated circuit device the memory cell array portion of which is made microscopic.
Another object of the invention is to provide a semiconductor integrated circuit device in which the resistance of plugs of peripheral circuit portions and a logic circuit is loared.
A further object of the invention is to provide a method for fabricating a semiconductor integrated circuit device which has capacitors of a DRAM, etc. that contribute to reduction in fabrication cost.
A still further object of the invention is to provide a method for fabricating a semiconductor integrated circuit device which is of such a structure that a capacitor is placed above a wiring layers without forming holes with a large aspect ratio and padding such holes with a conductive film.
To achieve the above objects, a semiconductor integrated circuit device of the invention is characterized in that a semiconductor body thereof includes peripheral circuit portions comprising an I/O control circuit portion and a decoder portion, and a memory cell array portion, wherein a diffused layer (source drain region) of an insulated gate field effect type transistor (select transistor) formed in the memory cell array portion is electrically connected with a lower electrode of a capacitor formed on a plurality of interlayer insulating films formed in layers on the transistor, through a plurality of plugs directly connected in sequence by penetrating each of the interlayer insulating films, and wherein a plurality of plugs formed in the peripheral circuit portions are mutually connected through wirings or contact pads for wiring.
Namely, as shown in
FIG. 3
, for example, a plurality of interlayer insulating films
8
,
12
,
15
, and
18
are formed in layers on a MOS transistor formed in a semiconductor substrate
1
and a storage capacitor is formed on the plurality of interlayer insulating films. A lower electrode
20
of the storage capacitor is electrically connected with a diffused layer
3
of the MOS transistor through a plurality of plugs
10
,
13
,
16
, and
19
directly connected in sequence by penetrating each of the plurality of interlayer insulating layers.
Since the plugs
10
,
13
,
16
, and
19
are directly connected in sequence without using the intermediary of contact pads, the occupied area of contact is reduced. Although the small connection area increases a little the resistance among the plugs
10
,
13
,
16
, and
19
, this is a trivial problem with the use as storage node contact plugs.
Moreover, according to the invention, the plurality of plugs
10
,
13
,
16
, and
19
are formed by penetrating each of the plurality of interlayer insulating films
8
,
12
,
15
, and
18
formed in layers. Forming a connection hole in a thick interlayer insulating film and forming a plug by padding the connection hole with metal increases the aspect ratio of the connection hole, making it difficult to form the connection hole and pad it with metal. According to the invention, however, for each of a plurality of thin interlayer insulating films instead of a thick interlayer insulating film, a connection hole is formed and metal is padded. Hence, the aspect ratio of each connection hole becomes small and the formation of connection holes and the padding by metal are extremely facilitated. Accordingly, it is easy to obtain such a device structure that a capacitor is placed above wiring layers.
On the other hand, in peripheral circuit portions, as shown in
FIG. 4
, because plugs
10
,
13
,
16
, and
19
are mutually connected through contact pads
11
,
14
, and
17
, respectively, connection resistance can be sufficiently loared and the peripheral circuit portions can obtain an adequate current. Yet, the memory cell array portion and the peripheral circuit portions can be formed simultaneously through identical proc
Fukuda Takuya
Kobayashi Nobuyoshi
Nakamura Yoshitaka
Saito Masayoshi
Antonelli, Terry, Stout & Krasu, LLP
Bowers Charles
Hiatchi Ltd.
Nguyen Thanh
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