Active solid-state devices (e.g. – transistors – solid-state diode – Point contact device
Reexamination Certificate
2001-09-28
2004-09-21
Deo, Duy-Vu (Department: 1765)
Active solid-state devices (e.g., transistors, solid-state diode
Point contact device
C257S002000, C257S390000, C257S401000
Reexamination Certificate
active
06794677
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method for fabricating the same. More particularly, it relates to technology for forming a linear pattern composed of the gate electrode and wires of a MOS transistor, or metal wires, and the like in a system LSI in which a group of elements having an extremely fine repetitive pattern, such as DRAMs (Dynamic Random Access Memories), can be merged.
As an example of a semiconductor integrated circuit device in which DRAMs are merged, a system LSI on which DRAMs having a capacity over 20 megabits are mounted has been mass-produced in recent years.
In the fabrication steps for a semiconductor integrated circuit device represented by the system LSI in which the mounting rate of memory circuits such as DRAMs, SRAMs (Static Random Access Memories), or ROMs (Read Only Memories) on a single semiconductor chip (rate of an area occupied by the memory circuits to an area of the entire chip; hereinafter also referred to as an area-occupying rate) differs according to usage or specifications, the formation of a mask pattern having not only unit circuits which are simply and repeatedly arranged therein but also a variety of layouts has been required.
There has conventionally been known a phenomenon in which the configuration or size of a pattern obtained by etching a target film by using a mask pattern (hereinafter referred to as a formed pattern) differs depending on a mask pattern layout, i.e., the placement of an element pattern.
As an example of the phenomenon, a pattern proximity effect occurring during the formation of a resist pattern in a photolithographic step can be listed. This is the phenomenon in which even a pattern having the same design configuration and the same design size has different configurations and sizes after it is formed depending on the degree of proximity between the pattern and a pattern adjacent thereto or on the configuration of the adjacent pattern.
As another example, there can be listed a loading effect or a microloading effect occurring in a dry etching step. The loading effect is a phenomenon in which an etching rate varies depending on the size of a total etched area of a semiconductor chip, which may slightly affect variations in pattern size. The microloading effect is a phenomenon in which, when a pattern laid out in a single semiconductor chip shows an arrangement which is locally sparse and dense, an etching rate differs locally due to the locally dense and sparse arrangement. That is, the etching rate for even the single chip differs from the portion thereof on which the pattern is sparsely placed to the portion thereof on which the pattern is densely placed, which also indirectly affects variations in pattern size.
To solve the foregoing problem of variations in pattern size depending on the mask pattern layout, there have conventionally been adopted such design rules as to correct variations in pattern size only at a portion of a mask where the pattern size is considered to vary remarkably depending on the mask pattern layout due to the proximity effect or the loading effect.
On the other hand, the fabrication of a system LSI in which DRAMs can be merged has used the same processing method or the same processing condition irrespective of the presence or absence of a mounted DRAM or of a DRAM area-occupying rate (the rate of an area occupied by the DRAMs to the area of an entire chip).
With the increasing miniaturization of the LSI, specifically as the size of an integrated circuit pattern is reduced to 0.25 &mgr;m or less, particularly to 0.15 &mgr;m or less, higher-precision size control has been required so that size variations resulting from difference in mask pattern layout are no more negligible.
FIG. 8
shows the frequency distribution of a CD (critical dimension) loss which is the difference between the size of a resist pattern prior to etching and the size of a completed gate electrode when the gate electrode is formed by dry etching by using the resist pattern as a mask in the fabrication of each of semiconductor integrated circuit devices on which 24 Mb DRAMs are mounted (hereinafter referred to as a DRAM mounted type) and a semiconductor integrated circuit device on which DRAMs are not mounted (hereinafter referred to as a DRAM unmounted type). The result shown in
FIG. 8
was obtained by using the same gate-electrode forming process in the fabrication of each of the DRAM mounted type and the DRAM unmounted type. Each of the CD losses was calculated by subtracting the size of the completed gate electrode from the size of the resist pattern prior to etching.
As shown in
FIG. 8
, mask-pattern-layout dependency is observed in pattern size though the same gate-electrode forming process was used to fabricate each of the types.
This indicates that, in accordance with the conventional method for fabricating a semiconductor integrated circuit device, the gate electrode size varies with difference in mask pattern layout associated with different types of semiconductor integrated circuit devices even if the same gate-electrode forming process is used. In other words, type dependency occurs in gate electrode size. As a result, the characteristics of a MOS transistor deviate from design specifications in a specified type of semiconductor integrated circuit device fabricated by using a specified mask, which causes the problem of a narrower operating margin. The problem cannot be ignored especially when the design rules are 0.18 &mgr;m or less.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore an object of the present invention to prevent a size variation resulting from difference in mask pattern layout during the formation of a linear pattern composed of the gate electrode and wires of a MOS transistor, or metal wires, and the like.
To attain the object the present inventors have examined the cause of size variations resulting from difference in mask pattern layout.
As a result the examination, the present inventors have found that, in a semiconductor integrated circuit device on which a logic circuit composed of a CMOS (Complementary Metal-Oxide Semiconductor) is mounted and a memory circuit such as a DRAM composed of the gate electrode and wires that are densely arranged is mounted, pattern size varies with the area-occupying rate of the memory circuit.
The present inventors have also found that the phenomenon in which size variations result from difference in mask pattern layout is different in nature from the foregoing loading effect which results from the size of the etched area, i.e., the area of the pattern. As is obvious from
FIG. 8
, the phenomenon is a phenomenon of novel nature in which the pattern size varies over the entire chip, which is also different from the microloading effect resulting from the in-chip local denseness and sparseness of the pattern.
As described above, the type dependency of the size of the formed gate electrode or the like results from the CD loss. On the other hand, a dry etching step currently performed uses an etching gas having a sidewall protecting effect (hereinafter referred to as a deposition gas) or forms an etching reaction product having the sidewall protecting effect to achieve anisotropic dry etching by preventing side etching. If a gate electrode is formed by performing dry etching with respect to a polysilicon film, a chlorine-containing gas, e.g., is used frequently as the etching gas and HBr gas is used frequently as the deposition gas. As a result, a sidewall protecting film composed of SiBr
4
, which is a reaction product between HBr and polysilicon and has low volatility, is formed on a sidewall of the polysilicon film. In the case of forming aluminium wires by performing dry etching with respect to an aluminium film, a CHF
3
gas has been used frequently as the deposition gas in recent years. The CHF
3
gas containing fluorine is a depositive gas added to form the sidewall protecting film but does not contribute to the etching of the aluminium film.
The present inve
Kawashima Koichi
Sakurai Yasuo
Tamaki Tokuhiko
Tateiwa Kenji
Deo Duy-Vu
McDermott & Will & Emery
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