Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2001-08-27
2004-07-06
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S054000, C257S355000
Reexamination Certificate
active
06760204
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor integrated circuit device and a method for designing the same, and more specifically to a semiconductor integrated circuit device that include insulated gate field effect transistors (IGFETs) (such as Metal-Oxide-Semiconductor (MOS) FET (Field Effect Transistor)) and a method of designing the same.
BACKGROUND OF THE INVENTION
As semiconductor device features becomes finer and the integration of such devices increases, an important concern can be electrostatic discharge (ESD). Electrostatic discharge can result when a static electricity, or the like, is discharged into or from a semiconductor device. ESD may result in damage to a semiconductor device, causing such a device to immediately fail, or have decreased reliability. One particular failure mechanism can be a breakdown of the gate dielectric in an insulated gate field effect transistor, such as the gate oxide of a metal-oxide-semiconductor FET.
ESD is believed to occur at various stages in a manufacturing process when semiconductor devices are handled and transported, for example.
Various models of the ESD breakdown phenomenon have been proposed, including a human body model (Human Body Model: HBM), a machine model (Machine Model: MM), and a charged device model (Charged Device Model: CDM).
In the HBM model, electric charges are generated, and then discharged to a device when a charged human makes contact with the device. In the MM model, electric charges are generated on a metal instrument, or the like, and then discharged to a semiconductor device when the instrument and device contact one another. In general, such a metal instrument can have a larger electrostatic capacitance than a human body, but also have a lower discharge resistance than a human body.
Using the above-mentioned models, semiconductor devices may be appraised for resistance/susceptibility to ESD events. For appraisal according to HBM and MM models, electric charges can be applied between two predetermined terminals of a device. In contrast, for appraisal according to a CDM model, a package and a chip of the device can be charged with electricity. Such charge can then be discharged to an outside location through terminals of the device.
To better understand the present invention, conventional approaches to semiconductor devices and ESD protection will be described below, including descriptions of a CDM model and a general counter measure to CDM type events.
Referring now to
FIG. 15
, an example of a semiconductor integrated circuit device is shown in a block diagram and designated by the general reference character
100
.
FIG. 15
shows various terminals and an internal circuit of a semiconductor integrated circuit device
100
.
As illustrated in
FIG. 15
, a semiconductor integrated circuit device includes a terminal
110
that is connected with a gate of a MOSFET
112
through an input resistance Rin
114
. A MOSFET
112
is illustrative of an internal circuit of a semiconductor device
100
. An input resistor
114
is illustrative of an input resistance and an input wiring resistance inherent in semiconductor device
100
.
A semiconductor device
100
also includes an electrostatic protective device, referred to herein as a clamping device
111
. A clamping device
111
is connected between terminal
110
and reference electric potential wiring
117
. A reference electric potential wiring
117
can be a ground (GND) wiring and/or a substrate electric potential wiring that may be operated at a different potential than GND. Electrostatic protective device
111
serves to prevent MOSFET
112
from being subjected to static electricity that is applied from the outside to terminal
110
. Such static electricity may result in a MOSFET
112
being damaged.
Electrostatic protective device
111
is generally provided to protect the semiconductor device
100
from the aforementioned human body model (HBM) and machine model (MM) type events. The structure and size of electrostatic protective device
111
are selected to sufficiently insulate the semiconductor device
100
from HBM and MM type ESD events.
Referring again to
FIG. 15
, a capacitor
120
is also shown. A capacitor
120
can designate the equivalent capacitance of a semiconductor device
100
with respect to earth GND, when such a semiconductor device is being tested according to the CDM model. Electric charges with a semiconductor device may be stored on a capacitor
120
.
During a test, terminal
110
is grounded through a CDM test switch
121
. In the CDM test, electric charges on the device (i.e., all electric charges over the entire chip) are discharged to ground from terminal
110
, through reference electric potential wiring
117
and electrostatic protective device
111
. Reference electric potential wiring
117
includes reference electric potential wiring resistance Rg
116
.
In addition, during a CDM type test, charge stored on a gate of MOSFET
112
can be discharged from terminal
110
to the ground. As noted above, charge on a gate of MOSFET
112
can constitute the charge on an internal circuit of a semiconductor device
100
. The electric charge stored on the gate of MOSFET
112
, that constitutes that of an internal circuit, can be substantially less than the charge discharged through the reference electric potential wiring
117
. Consequently, charge on the gate of MOSFET
112
can be discharged to ground in a relatively shorter time that a reference electric potential wiring
117
.
Such a faster discharge time may result in a relatively large electric potential developing between a gate of MOSFET
112
, which has been discharged, and a source of MOSFET
112
, which may be at the still discharging potential of reference electric potential wiring
117
. Unless addressed, such an electric potential may breakdown the gate oxide film of a MOSFET
112
, or otherwise damage a MOSFET
112
.
To preventing such a breakdown there is generally provided a CDM protective device, also referred to as clamp device
113
, that is in close vicinity to a MOSFET
112
, between the gate and source of MOSFET
112
.
A prior art technique for addressing ESD is shown in Electrical Overstress/Electrostatic Discharge Symposium Proceeding September 27-29, pp.220-227, 1988, referred herein as Reference 1. Reference 1 discloses that an input resistance, such as that shown as Rin
114
in
FIG. 15
, is effective for addressing HBM and MM type ESD events.
It is noted that an increase of an input resistance, such as Rin
114
in
FIG. 15
, may adversely affect circuit performance. Thus, there can be a tradeoff relationship between ESD protection and circuit performance. For this reason, it can be necessary to select an optimum value of an input resistance, Rin
114
, that accounts for such a tradeoff relationship.
Additional prior art techniques are shown in Electrical Overstress/Electrostatic Discharge Symposium Proceeding, pp. 116 to 123, 1999 (referred to herein as Reference 2). Reference 2 discloses a relationship between an input resistance, such as Rin
114
of
FIG. 15
, a reference electric potential wiring resistance, such as Rg
116
in
FIG. 15
, and CDM insulation.
Referring now to
FIG. 16
, a simulation result of ESD for a device, such as that shown in
FIG. 15
is shown.
FIG. 16
shows how an electric potential difference (Vox) between the gate and the source of MOSFET
112
can vary over time during an ESD event. In particular,
FIG. 16
shows how the electric potential differences (Vox) changes in response to the action of CDM protective device
113
during CDM testing. Three curves are shown; curves (a) to (c).
Curve (a) shows a change in Vox when CDM protective device
113
is completely clamped. The response of Vox is shown to sharply change in curves (b) and (c) as the operation of CDM protective device
113
varies. Curve (c) in particular demonstrates a Vox response where MOSFET
112
is destroyed during the CDM test.
It is noted that the value of Vox that can result in the destruction of a MOSFET
112
varies a
Furuta Hiroshi
Hayano Kiminori
Hayashida Yoko
NEC Corporation
Nguyen Danny
Sako Bradley T.
Sircus Brian
Walker Darryl G.
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