Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-02-15
2001-05-15
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S331000
Reexamination Certificate
active
06232819
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of receiving a low-amplitude signal and, more particularly, to an input circuit for transmitting a signal between semiconductor integrated circuit devices as a low-amplitude signal and a method of receiving such a low-amplitude signal.
BACKGROUND OF THE INVENTION
In TTL (Transistor-Transistor-Logic) level or CMOS (Complementary Metal-Oxide-Semiconductor) level arrangements widely used for interfaces between CMOS semiconductor integrated circuit devices, irregular reflections are caused at both ends of a signal transmission line, so that it is known that data transfer frequencies are limited in performance to 60 MHz to 100 MHz at most. On the other hand, in pseudo ECL (Emitter Coupled Logic) and GTL (Gurnning Transceiver Logic) arrangements, the data transfer frequency is raised by connecting a terminating resistor to the end of a signal transmission line to prevent the reflection of the waveform.
However, in order to reduce power consumption, the signal amplitude is limited to about 0.8 V (volt) relative to 5 V (volt) or 3.3 V (volt) of the operating or the supply voltage of a semiconductor integrated circuit device.
A pseudo ECL arrangement is described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 1, February 1988, PP. 59-67. A GTL arrangement is disclosed in U.S. Pat. No. 5,023,488 (Jan. 11, 1991).
SUMMARY OF THE INVENTION
Along with the advancement in micro fabrication technology for semiconductor integrated circuit elements, attempts for enhancing the speed of CMOS semiconductor integrated circuit devices are being made. As the operating speed of circuits internal to semiconductor integrated circuit devices increases, the present inventors came to notice that the data transfer speed between semiconductor integrated circuit devices would eventually lag behind the operating speed, bottlenecking the enhancement of the performance of an entire system. The present inventors reviewed the data transfer between semiconductor integrated circuit devices to achieve the present invention.
It is therefore an object of the present invention to provide a structure with a simple construction for providing high-speed data transfer between semiconductor integrated circuit devices.
It is a further object of the present invention to provide a method of receiving a low-amplitude signal at a high speed in a semiconductor integrated circuit device.
Other and further objects, features, and advantages of the invention will appear more fully from the following description taken in connection with the accompanying drawing.
The present invention will be outlined in one aspect as follows.
Namely, an input buffer or an input circuit in the semiconductor integrated circuit device is provided that has a latch circuit for receiving an input signal entered in synchronization with a clock signal and provided with a low amplitude relative to an amplitude between a first and a second supply voltage for the semiconductor integrated circuit device and holding this received signal with its amplitude kept correspondingly small.
In carrying out the invention, and according to another aspect thereof, there is provided a method of receiving a low-amplitude signal wherein, when signal transmission is performed between at least a pair of semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an amplitude between a first and a second supply voltage for the semiconductor integrated circuit devices, a received signal is held on the receiving semiconductor integrated circuit device in synchronization with the clock signal with the small signal amplitude kept without change. Then, the received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit and provided to a succeeding latch circuit in the receiving semiconductor integrated circuit device.
REFERENCES:
patent: 4181865 (1980-01-01), Kohyama
patent: 4511810 (1985-04-01), Yukawa
patent: 4558241 (1985-12-01), Suzuki et al.
patent: 4785206 (1988-11-01), Hoshi
patent: 4910713 (1990-03-01), Madden et al.
patent: 4943738 (1990-07-01), Hoshi
patent: 4973864 (1990-11-01), Nogami
patent: 5023475 (1991-06-01), Ducourant
patent: 5023488 (1991-06-01), Gunning
patent: 5148061 (1992-09-01), Hsueh et al.
patent: 5461333 (1995-10-01), Condon et al.
patent: 5530392 (1996-06-01), Runas et al.
patent: 5534812 (1996-07-01), Cao et al.
patent: 5594368 (1997-01-01), Usami
patent: 2-37823 (1990-02-01), None
Chappell et al., “Fast CMOS ECL Receivers with 100-nV Worst-Case Sensitivity”, IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 59-67.
Koide Kazuo
Takahashi Toshiro
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lam Tuan T.
LandOfFree
Semiconductor integrated circuit device and low-amplitude... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and low-amplitude..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and low-amplitude... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2532229