Semiconductor integrated circuit device and digital...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S1540PB

Reexamination Certificate

active

06972585

ABSTRACT:
In a semiconductor integrated circuit device having a DRAM30, the DRAM30has an internal refresh period measuring circuit20. Supplied with a test mode command as an external command, a command decode portion32delivers a test mode signal TM1to the internal refresh period measuring circuit20, supplies external clocks CLK as reference clocks ICLK to the internal refresh period measuring circuit20, and thereafter activates a self-refresh control circuit33. When activated, the self-refresh control circuit33delivers an internal oscillation signal LOSC or OSC having a self-refresh period to the internal refresh period measuring circuit20. The internal refresh period measuring circuit20counts the number of the reference clocks supplied during a self-refresh period of the internal oscillation signal.

REFERENCES:
patent: 6247138 (2001-06-01), Tamura et al.
patent: 6665225 (2003-12-01), Tsujino
patent: S60-111971 (1985-06-01), None
patent: H08-184460 (1996-07-01), None
patent: 2002-056671 (2002-02-01), None

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