Semiconductor integrated circuit device and data writing...

Details Semiconductor integrated circuit device and data writing... Semiconductor integrated circuit device and data writing...

2001-12-07

2004-05-25

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189020, C365S226000

Reexamination Certificate

active

06741518

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data writing into a memory cell in a semiconductor integrated circuit device. More particularly, the present invention relates to reduction of noise caused by a writing operation.
2. Description of the Related Art
With advancement of recent computer technology, as in depicting of a three-dimensional moving picture, there has been a need for a memory applicable to graphics use in which an address cycle irregularly changes. As a result, a high speed random access performance is required irrespective of a data readout cycle or a write cycle. However, as in a dynamic random access memory (hereinafter, referred to as a DRAM) or a synchronous type semiconductor memory device represented by a synchronous DRAM (hereinafter, referred to as a SDRAM), in a memory of such type multiplexing row addresses and column addresses, thereby inputting them at a separate timing, a high speed random access performance of such type cannot be achieved.
Because of this, as a high speed memory achieving a high cycle time performance of a static random access memory (hereinafter, referred to as a SRAM) while utilizing high integrity of DRAM or SDRAM, there has been devised a memory that determines a readout cycle or a write cycle by inputting addresses without multiplexing them, and by one command signal. A fast cycle random access memory (FC RAM (registered trademark)) is obtained as a typical device.
A memory cell section
1000
shown in
FIG. 20
is a specific example showing a configuration of a high speed memory. Required constituent elements are excerpted for the purpose of explanatory convenience, and part of the high speed memory is shown. Memory cells Ta to Td are connected to bit lines /BL
1
, /BL
2
, BL
1
, and BL
2
. The data stored in the memory cell Ta to Td is read out as a stored charge, and the read data is redistributed into the bit lines /BL
1
, /BL
2
, BL
1
, or BL
2
. Then, bit line pair BL
1
and /BL
1
and bit line pair BL
2
and /BL
2
are paired, and the data are amplified by means of sense amplifiers SA and SAM. The amplified data is posted to data buses DB and /DB via a pair of column switches TN
1
and TN
2
and a pair of column switches TN
3
and TN
4
, and amplified by means of read amplifier RA to output (Dout). Conversely, input data Din is amplified by means of a write amplifier WA, and the amplified data is stored by being stored as a charge in the memory cells Ta to Td from the data buses DB and /DB via bit lines BL
1
, /BL
2
, BL
1
, or BL
2
.
Selection of the memory cells Ta to Td to be connected to the bit lines /BL
1
, /BL
2
, BL
1
, or BL
2
is as follows. First, a row control circuit RC receives an internal command signal CMD generated in accordance with a readout or write cycle determined by an external one command signal (not shown), and an active signal ACT and a precharge signal PRE are output. Of these signals, these sent to a word decoder WD activates or deactivates the word decoder WD, and initiates word lines WL and WLM. In addition, those input to a sense amplifier signal circuit SC activates the same amplifiers SA and SAM to control an activation signal LE.
Apart from the shown memory cells Ta and Td, a number of memory cells (not shown) are connected to bit lines BL
1
and /BL
1
or the like, and these memory cells are sequentially selected by means of a word line (not shown) selected by the word decoder WD based on the row address signals ADRn (n=1, 2, . . . ). Therefore, it is required to short bit line pair BL
1
and /BL
1
or the like every memory cell access, and precharge these pairs at a predetermined voltage (VPR). This precharge operation is carried out by bit line short circuits BS and BSM. The bit line short circuits BS and BSM are controlled by a bit line short signal BRS from a bit line short signal circuit BSS based on the active signal ACT and the precharge signal PRE from the row control circuit RC.
In addition, the column switch signal circuits CS and CSM receive control signals WC and WCD output from a column control circuit CC based on an internal command signal CMD and a column address signals ADCn (n=1, 2, . . . ), and outputs switch signals CL
1
and CL
2
as required according to the column address signals ADCn (n=1, 2, . . . ). In this manner, the column switch TN
1
to TN
4
are conductive or nonconductive.
It is required to short and precharge the data buses DB and /DB by every readout or write cycle as in the bit line pair BL
1
and /BL
1
or the like. This precharge operation is carried out by a data bus short circuit DBS. The data bus short circuit DBS is controlled by a data bus short signal CPR from a data bus short signal circuit DBSS based on the control signals WR and WCD from the column control circuit CC.
FIG. 21
is a time chart showing a write operation for a memory cell section
1000
of the prior art. At a time t
0
, an internal command signal CMD is output, a row control circuit RC is initiated, and an active signal ACT is output (time t
1
). A bit line short signal BRS is deactivated by this signal ACT, and bit line precharge period terminates (time t
1
). In addition, a word line WL is selected by means of a word decoder WD, and memory cells Tc and Td are connected to the bit lines BL
1
and BL
2
(time t
2
). In this manner, the stored charge of the memory cells Tc and Td is started to be redistributed into the bit lines BL
1
and BL
2
.
FIG. 21
shows a case in which data “1” and “0” are written into the memory cells Tc and Td. Therefore, the bit line BL
1
rises from a precharge voltage VPR, and conversely, the bit line BL
2
falls.
In a process in which the stored charge from the memory cells Tc and Td selected by the word line WL is redistributed to each of the bit lines BL
1
and BL
2
, a second internal command signal CMD is issued. This second command signal CMD is an internal command signal internally generated in the case where an external one command (not shown) is a write command. After this signal has been output, the column control circuit CC is initiated, and a control signal WR is output. In addition, a data bus short signal circuit DBSS deactivates a data bus short signal CPR, and terminates a precharge period of the data buses DB and /DB. In addition, this circuit activates a write amplifier WA by means of an activation signal WAE, and amplifies write data between data buses DB and /DB (time t
3
).
At a time t
4
delayed from the time t
3
, the control signal WC output from the column control circuit CC works as trigger to make a switch signal CL
1
output from a column switch signal circuit CS that corresponds to column address signals ADCn (n=1, 2, . . . ) active, and make column switches TN
1
and TN
2
conductive. As a result, the data buses DB and /DB and the bit lines BL
1
and /BL
1
are interconnected to each other, and the preceding write data amplified in the data buses DB and /DB are written into the bit lines BL
1
and /BL
1
.
A potential difference between bit line pair BL
1
and /BL
1
is amplified by being driven by the write amplifier WA. On the other hand, the stored charge of the memory cell Td or the like is redistributed between the memory cell Td or the like and bit line BL
2
or the like into the other bit line pair containing the adjacent bit line pair BL
2
and /BL
2
. The bit line /BL
2
or the like in which a memory cell is not selected is kept to be a precharge voltage VPR, and thus, a potential difference between the bit line pair BL
2
and /BL
2
gradually increases. Then, after this potential difference has reached the amplification sensitivity of the sense amplifier SAM, an activation signal LE is set to its logical level “high” by means of the sense amplifier signal circuit SC. As a result, the sense amplifier SAM is driven, and the bit line pair BL
2
and /BL
2
is amplified (time t
5
). At this time, a potential difference between the bit line pair BL
2
and /BL
2
is about some tens of mV. The memory cells Ta to Td are memory cells of such typ

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