Semiconductor integrated circuit device and a method of...

Details Semiconductor integrated circuit device and a method of... Semiconductor integrated circuit device and a method of...

2009-08-23

2011-10-25

Tran, Thien F (Department: 2895)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C438S129000

Reexamination Certificate

active

08043900

ABSTRACT:
To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells.In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.

REFERENCES:
patent: 7325214 (2008-01-01), Liao
patent: 7326595 (2008-02-01), Kuroki
patent: 2006/0202231 (2006-09-01), Yamamoto
patent: 11-135734 (1999-05-01), None
patent: 2006-228982 (2006-08-01), None
patent: 2006-253375 (2006-09-01), None
patent: 2007-73885 (2007-03-01), None

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