Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2008-07-08
2008-07-08
Lee, Eugene (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257SE21546, C257S506000
Reexamination Certificate
active
07397104
ABSTRACT:
A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
REFERENCES:
patent: 5233212 (1993-08-01), Ohi et al.
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5559048 (1996-09-01), Inoue
patent: 5672529 (1997-09-01), Kato et al.
patent: 5674775 (1997-10-01), Ho et al.
patent: 5882982 (1999-03-01), Zheng et al.
patent: 5910018 (1999-06-01), Jang
patent: 5937309 (1999-08-01), Chuang
patent: 6107134 (2000-08-01), Lu et al.
patent: 6166417 (2000-12-01), Bai et al.
patent: 6175140 (2001-01-01), Kajiyama
patent: 6211546 (2001-04-01), Kato et al.
patent: 6238999 (2001-05-01), Dickerson et al.
patent: 6420268 (2002-07-01), Moore et al.
patent: 6424011 (2002-07-01), Assaderaghi et al.
patent: 2-260660 (1990-10-01), None
patent: 4-303942 (1992-10-01), None
patent: 7-74164 (1995-03-01), None
patent: 8-97277 (1996-04-01), None
patent: 08-330532 (1996-12-01), None
patent: 09-172064 (1997-06-01), None
patent: 10-144878 (1998-05-01), None
patent: 10-144886 (1998-05-01), None
patent: 11-17139 (1999-01-01), None
patent: 11-74475 (1999-03-01), None
patent: 11-97648 (1999-04-01), None
patent: 2000-31264 (2000-01-01), None
patent: 2000-68367 (2000-03-01), None
Yeh et al., “A Novel Shallow Trench Isolation with Mini-Spacer Technology” Extended Abstracts of the 1998 Int'l Conference on Solid State Devices and Materials, Hiroshima, 1998, pp. 98-99.
Horibe Shinichi
Ichizoe Hiroyuki
Ikeda Shuji
Ishitsuka Norio
Kojima Masayuki
Antonelli, Terry Stout & Kraus, LLP.
Elpida Memory Inc.
Lee Eugene
LandOfFree
Semiconductor integrated circuit device and a method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and a method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and a method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2809744