Semiconductor integrated circuit device and a method for manufac

Details Semiconductor integrated circuit device and a method for manufac Semiconductor integrated circuit device and a method for manufac

1988-03-31

1990-05-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 59, 437 41, 357 43, H01L 21265

Patent

active

049218115

ABSTRACT:
An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

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