Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Patent
1995-03-24
1998-06-16
Tung, Kee M.
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
345511, 345517, G06F 1576
Patent
active
057678650
ABSTRACT:
Two frame buffer memories are used. Depth coordinates are stored in a data bank memory of the first frame buffer memory. A comparing unit makes comparison between the depth coordinate of an image data currently displayed and the newly input depth coordinate, and thereby outputs a comparison result signal from a comparison result signal output terminal. In the second frame buffer memory, color data is stored in a data bank memory, and the comparison result signal sent from the first frame buffer memory is input via a comparison result signal input terminal. An image processing unit performs blending processing on the color data in response to the comparison result signal, and rewrites the color data.
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"Samsung Proposes A Dual Port 1 Mbyte Frame Buffer", JEDEC May 19, 1993, Samsung Proposal.
Inoue Kazunari
Matsuoka Hideto
Mitsubishi Denki & Kabushiki Kaisha
Tung Kee M.
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