Static information storage and retrieval – Addressing – Sync/clocking
Patent
1993-12-14
1995-05-02
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sync/clocking
36523008, 36523003, 365194, 327141, G11C 800
Patent
active
054126150
ABSTRACT:
This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.
REFERENCES:
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5206833 (1993-04-01), Lee
patent: 5265063 (1993-11-01), Kogure
Kamata Shinnosuke
Noro Hiromi
Okajima Yoshinori
Fujitsu Limited
Hoang Huan
Popek Joseph A.
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