Patent
1984-07-30
1986-09-09
Larkins, William D.
357 239, 357 59, H01L 2978
Patent
active
046112375
ABSTRACT:
A MOS transistor integrated circuit device has at least one interconnection layer crossing the source and drain regions of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer is formed on the surface of at least one of the source and drain regions of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes and electrically insulated from the interconnection layer.
REFERENCES:
patent: 3964092 (1976-06-01), Wadham
patent: 4163246 (1979-07-01), Aomura et al.
patent: 4222062 (1980-09-01), Trotter et al.
patent: 4329706 (1982-05-01), Crowder et al.
Japanese Journal of Applied Physics, vol. 18, No. 3, Mar. 1979, Tokyo, Japan: M. Hirabayashi, pp. 581-587.
Natori Kenji
Ogura Mitsugi
Ohuchi Kazunori
Larkins William D.
Tokyo Shibaura Denki Kabushiki Kaisha
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