Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1993-08-19
1995-08-08
Nguyen, Viet Q.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523001, 36523002, 36523006, 365231, 36518908, H01L 2710
Patent
active
054405211
ABSTRACT:
A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat. At least some of wiring lines connected to each sense amplifier are formed in a wiring layer in which Y-selection lines are formed. The Y-selection lines are extended in gaps between the sense amplifiers.
REFERENCES:
patent: 5018100 (1991-05-01), Yanagisawa
patent: 5021998 (1991-06-01), Suzuki et al.
patent: 5150325 (1992-09-01), Yanagisawa et al.
"16-Mbit DRAM Specifications Will be Decided on For Sample Shipments in 1990", Nikkei Microdevices, Mar. 1, 1988, pp. 67-81. (with translation).
Aoyagi Hidetomo
Hoshida Akihiko
Ishii Kyoko
Koyama Yoshihisa
Miyatake Sinichi
Hitachi , Ltd.
Hitachi Hokkai Semiconductor Ltd.
Hitachi VLSI Engineering Corp.
Nguyen Viet Q.
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