Semiconductor integrated circuit device

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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Details

C257S204000, C257S288000, C257S369000, C716S030000

Reexamination Certificate

active

07737472

ABSTRACT:
A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.

REFERENCES:
patent: 6987293 (2006-01-01), Sakamoto et al.
patent: 7132323 (2006-11-01), Haensch et al.
patent: 2007/0141766 (2007-06-01), Sekido et al.
patent: 2003-133416 (2003-05-01), None
patent: 2007-165670 (2007-06-01), None

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