Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2008-11-12
2010-12-07
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S230010, C365S230060, C365S230090, C365S189050, C365S189040
Reexamination Certificate
active
07848177
ABSTRACT:
The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.
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Kajiyama Shinya
Kasai Hideo
Mizuno Makoto
Sekiguchi Tomonori
Shinagawa Yutaka
Le Thong Q
Miles & Stockbridge P.C.
Renesas Electronics Corporation
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