Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-12-12
2008-08-12
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S226000
Reexamination Certificate
active
07411805
ABSTRACT:
A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
REFERENCES:
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5619148 (1997-04-01), Guo
patent: 5754838 (1998-05-01), Shibata et al.
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 5883534 (1999-03-01), Kondoh et al.
patent: 5923198 (1999-07-01), Fujioka
patent: 5926053 (1999-07-01), McDermott et al.
patent: 5936441 (1999-08-01), Kurita
patent: 5943285 (1999-08-01), Kohno
patent: 5953284 (1999-09-01), Baker et al.
patent: 5990714 (1999-11-01), Takahashi
patent: 6041013 (2000-03-01), Kohno
patent: 6069508 (2000-05-01), Takai
patent: 6078514 (2000-06-01), Takemae et al.
patent: 6081142 (2000-06-01), Douchi et al.
patent: 6157688 (2000-12-01), Tamura et al.
patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6172537 (2001-01-01), Kanou et al.
patent: 6191632 (2001-02-01), Iwata
patent: 6194932 (2001-02-01), Takemae et al.
patent: 6222406 (2001-04-01), Noda et al.
patent: 6222792 (2001-04-01), Hanzawa et al.
patent: 6265903 (2001-07-01), Takahashi
patent: 6269051 (2001-07-01), Funaba et al.
patent: 6281725 (2001-08-01), Hanzawa et al.
patent: 6288585 (2001-09-01), Bando et al.
patent: 6304117 (2001-10-01), Yamazaki et al.
patent: 6313674 (2001-11-01), Akita et al.
patent: 6336901 (2002-01-01), Itonaga et al.
patent: 6346843 (2002-02-01), Takahashi
patent: 6373303 (2002-04-01), Akita
patent: 6377511 (2002-04-01), Okuda et al.
patent: 6400643 (2002-06-01), Setogawa
patent: 6417715 (2002-07-01), Hamamoto et al.
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6452859 (2002-09-01), Shimano et al.
patent: 6463008 (2002-10-01), Okuda et al.
patent: 6518813 (2003-02-01), Usui
patent: 6577181 (2003-06-01), Takahashi et al.
patent: 6594197 (2003-07-01), Okuda et al.
patent: 6603687 (2003-08-01), Jun et al.
patent: 6621352 (2003-09-01), Matsumoto et al.
patent: 6703879 (2004-03-01), Okuda et al.
patent: 6754133 (2004-06-01), Morita et al.
patent: 2001/0017558 (2001-08-01), Hanzawa et al.
patent: 2001/0021953 (2001-09-01), Nakashima
patent: 2001/0052808 (2001-12-01), Hamamoto et al.
patent: 2002/0008558 (2002-01-01), Okuda et al.
patent: 2002/0008589 (2002-01-01), Lanoman et al.
patent: 2002/0033737 (2002-03-01), Staszewski et al.
patent: 2002/0180500 (2002-12-01), Okuda et al.
patent: 2003/0123597 (2003-07-01), Cho
patent: 2-90666 (1990-03-01), None
patent: 10-171774 (1998-06-01), None
patent: 11-31024 (1999-02-01), None
patent: 11-55145 (1999-02-01), None
patent: 11-86546 (1999-03-01), None
patent: 11-205129 (1999-07-01), None
patent: 11-214986 (1999-08-01), None
patent: 2000-124796 (2000-04-01), None
patent: 2000-183730 (2000-06-01), None
patent: 2000-188540 (2000-07-01), None
patent: 2001-1332086 (2001-11-01), None
patent: 1999-13264 (2001-04-01), None
patent: 1999-66713 (2001-09-01), None
patent: 1999-66735 (2002-01-01), None
Johnson et al., “A Variable Delay Line PLL for CPU-Coprocessor Synchronization”,IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1218-1223, Oct. 1998.
Kokubo Masaru
Miyashita Hiroki
Nakagome Yoshinobu
Okuda Yuichi
Yahata Hideharu
Miles & Stockbridge P.C.
Nguyen Viet Q
Renesas Technology Corp.
LandOfFree
Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4012557