Semiconductor integrated circuit device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185230, C365S230060

Reexamination Certificate

active

07423909

ABSTRACT:
A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected.

REFERENCES:
patent: 5359572 (1994-10-01), Sato et al.
patent: 5943289 (1999-08-01), Ahn et al.
patent: 6515905 (2003-02-01), Hikida
patent: 2004-206745 (2002-12-01), None

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