Semiconductor integrated circuit device

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000, C257S362000

Reexamination Certificate

active

10827442

ABSTRACT:
An inventive semiconductor integrated circuit device includes: an external connection terminal1; an electrostatic discharge protection circuit2; an output circuit3; an output prebuffer circuit4; an input prebuffer circuit5; an internal circuit41; an inter-power supply electrostatic discharge protection circuit6; and a gate voltage control circuit7. The gate voltage control circuit7has a capacitor25and a resistor26, and the inter-power supply electrostatic discharge protection circuit6has an NMIS transistor24. When a positive surge is applied to the external connection terminal1, the gate potential of the NMIS transistor24is also increased. Thus, the NMIS transistor24is turned on, and the positive electrical charge supplied to the external connection terminal1is discharged toward a ground line23.

REFERENCES:
patent: 6437407 (2002-08-01), Ker et al.
patent: 6455902 (2002-09-01), Voldman
patent: 6552886 (2003-04-01), Wu et al.
patent: 6920026 (2005-07-01), Chen et al.
patent: 7-22617 (1995-01-01), None
patent: 07-503599 (1995-04-01), None
patent: 08-055958 (1996-02-01), None
patent: 08-097362 (1996-04-01), None
patent: 10-209292 (1998-08-01), None
patent: 2003-031672 (2003-01-01), None
patent: WO 93/15541 (1993-08-01), None

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