Patent
1990-03-20
1992-01-14
James, Andrew J.
357 43, 357 236, H01L 2702
Patent
active
050815156
ABSTRACT:
A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.
REFERENCES:
patent: 4845544 (1989-07-01), Shimizu
patent: 4887144 (1989-12-01), Cook et al.
Asayama Kyoichiro
Kobayashi Yutaka
Miyazawa Hideyuki
Miyazawa Hiroyuki
Murata Jun
Dang Hung Xuan
Hitachi , Ltd.
James Andrew J.
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