Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2007-01-30

2007-01-30

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000, C361S091500

Reexamination Certificate

active

11081669

ABSTRACT:
A semiconductor integrated circuit of the present invention includes, between a power line1and a ground line2, an NMIS transistor3capable of supplying fixed signals with low and high levels to the outside, an NMIS transistor6having a source connected to a gate of the NMIS transistor3, a PMIS transistor7having a drain connected to a gate of the NMIS transistor6, and an ESD protection power clamp circuit14. If a surge is applied to the power line1, the ESD protection power clamp circuit14is clamped to pass the surge to the ground line. While the surge is passed, the potential of the power line1rises to turn on the three transistors3, 6, and7. At this time, the NMIS transistor6and the PMIS transistor7can reduce the gate potential of the NMIS transistor3lower than the potential of the power line1.

REFERENCES:
patent: 4754158 (1988-06-01), Halberstein
patent: 5978192 (1999-11-01), Young et al.
patent: 6072682 (2000-06-01), Ravanelli et al.
patent: 6614633 (2003-09-01), Kohno
patent: 7-086906 (1995-03-01), None
patent: 07-086906 (1995-03-01), None
Adel S. Sedra and Kenneth C. Smith, “Microelectronics Circuits”, 1987, CBS College Publishing, Second Edition, pp. 342-410.

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